1. 23 Nov, 2012 1 commit
  2. 21 Nov, 2012 1 commit
  3. 20 Nov, 2012 1 commit
  4. 14 Jun, 2012 2 commits
  5. 05 Jun, 2012 1 commit
  6. 23 May, 2012 1 commit
    • Alexander Potashev's avatar
      RT78427. lpc1850-eval: Add support for Hitex LPC1850 Eval board · 40aa1110
      Alexander Potashev authored
       * Add Makefile target `lpc1850-eval_config`.
       * Set the system prompt to `LPC1850-EVAL> `.
       * Change CONFIG_MEM_NVM_LEN from 128 KBytes to 96 KBytes to match the
      size of the largest continuous region of internal SRAM on LPC1850.
       * Adjust clock configuration for the 180MHz maximum core clock rate on
      LPC1850: set the PLL1 multiplier value to 15.
       * Adjust SDRAM timings for the 180MHz maximum core clock rate on
      LPC1850.
       * Adjust NOR flash timings for the 180MHz maximum core clock rate on
      LPC1850.
       * Change default MAC address and IP address of the board defined in the
      U-Boot environment.
      40aa1110
  7. 22 May, 2012 1 commit
  8. 11 May, 2012 1 commit
    • Alexander Potashev's avatar
      RT77744. lpc4350: Support booting from 16-bit external NOR flash · 9942ae92
      Alexander Potashev authored
       * The Boot ROM bootloader loads only the first 32KBytes of U-Boot image
      from the external 16-bit NOR flash. We make U-Boot load the remaining
      contents of the image.
       * Put all function and data used for bootstrapping in the beginning
      of the U-Boot image in sections `.lpc18xx_image_top_text` and
      `.lpc18xx_image_top_data`.
       * Configure the boot pins to determine the boot source if the relevant
      fields in the One-Time Programmable memory are not set.
       * Configure the remaining EMC pins before reading the whole U-Boot
      image. The Boot ROM bootloader forgets to configure some EMC pins.
       * Reload the U-Boot image from NOR flash only when boot source is
      `EMC 16-bit`.
      9942ae92
  9. 03 May, 2012 3 commits
    • Alexander Potashev's avatar
      RT77744. lpc4350-eval: NOR flash support · b79aa072
      Alexander Potashev authored
       * Reuse the code from EA-LPC1788's NOR flash support;
       * Improve NOR flash timings;
       * Place U-Boot environment at address 0x20000 (128 KBytes) in NOR
      flash. We will store U-Boot image in the first 128 KBytes of NOR flash
      when booting from NOR flash.
       * Place Linux kernel image at address 0x40000 (256 KBytes) in NOR
      flash. We will store U-Boot image and U-Boot environment in the first
      128 KBytes of NOR flash.
      b79aa072
    • Alexander Potashev's avatar
      RT77744. lpc4350-eval: Ethernet support · 791d3ebe
      Alexander Potashev authored
       * Write a custom Ethernet driver for LPC18xx/LPC43xx. We know the
      Ethernet module is compatible with STM32F, but we do not want to spend
      time right now to merge these drivers.
       * Use Ethernet MII mode.
       * Store Ethernet DMA buffers and buffer descriptors in a free region of
      internal SRAM.
      791d3ebe
    • Alexander Potashev's avatar
      RT77744. lpc4350-eval: Configure EMC for SDRAM · 6a2c27cd
      Alexander Potashev authored
       * Use M4_CLK/2 = 102MHz for SDRAM clock;
       * Use best-performance timings for SDRAM.
      6a2c27cd
  10. 27 Apr, 2012 1 commit
    • Alexander Potashev's avatar
      RT77788. k70-som: Set DDR setting R2RSAME to 3 to avoid memory corruptions · 2b018150
      Alexander Potashev authored
       * When Ethernet and/or LCD are extensively utilized, the DDR controller send
      command to the memory chip very often, so that sometimes these commands go
      back-to-back to one another. In this situation the value of the R2RSAME
      parameter is taken into account by the DDR controller.
       * The necessary value for CR37[R2RSAME] was found experimentally. The K70
      Reference Manual is very unclear on the exact meanings of delays set by the
      fields of the DDR_CR37 register (including R2RSAME).
      2b018150
  11. 24 Apr, 2012 1 commit
    • Alexander Potashev's avatar
      RT77744. lpc4350-eval: Basic port · 55246688
      Alexander Potashev authored
      Support the following features:
       * Serial console on USART0.
       * Common pin configuration functions (needed for USART0).
       * Clock configuration: The Cortex-M4 core runs at 204 MHz.
       * `cptf` command is technically available, but has no effect since there is no
      internal flash on LPC18x0/LPC43x0 MCUs.
       * The lowest SRAM region (128 KB at 0x10000000) is reserved for the currently
      running U-Boot image.
      55246688
  12. 20 Apr, 2012 2 commits
  13. 11 Apr, 2012 1 commit
    • Alexander Potashev's avatar
      RT77788. k70-som: Add support for the Emcraft K70-SOM + SOM-BSB platform · 065d7e55
      Alexander Potashev authored
       * Add Makefile target `k70-som_config`.
       * Start K70-SOM board support code by cloning off the TWR-K70F120M
      board-specific code.
       * Update DDR controller configuration to interact with the LPDDR memory chip.
      Update timings for a 120 MHz DDR clock.
       * Remove configuration of pins NFC_D8..NFC_D15, they are not used by 8-bit NAND
      flashes.
       * Optionally support 8-bit NAND flashes in the `fsl_nfc.c` driver.
       * Set correct size of RAM (64 MB).
       * Do not configure the LCD clock, because we do not support LCDs with K70-SOM
      yet.
       * Update U-Boot prompt, IP address, MAC address, bootargs, hostname.
      065d7e55
  14. 09 Apr, 2012 1 commit
    • Alexander Potashev's avatar
      RT76276. Add support for STMicroelectronics STM3240G-EVAL board · f271a6db
      Alexander Potashev authored
      * Clone the board-specific files from those used for the STM3220G-EVAL board.
      * Change STM3220G-EVAL to STM3240G-EVAL where appropriate.
      * cpu/arm_cortexm3/stm32/clock.c: Add support for clock rates up to 168 MHz.
      * Ethernet driver: Implement us/ms delays not tied to CPU clock rate.
      * Ethernet driver: Add `stm_phy_wait_busy()` to reduce code duplication.
      * Raise system clock rate from 120 MHz to 168 MHz.
      * Update PSRAM timings.
      * Disable the PSRAM Synchronous Burst Mode.
      f271a6db
  15. 30 Mar, 2012 1 commit
  16. 29 Mar, 2012 1 commit
    • Alexander Potashev's avatar
      RT77452. Add support for Emcraft's LPC-LNX-EVB board · 0b0a296c
      Alexander Potashev authored
       * Add Makefile target `lpc-lnx-evb_config`.
       * Configure one more EMC address pin on LPC-LNX-EVB (in comparison to
      EA-LPC1788) to make all 16 MBytes of NOR Flash work.
       * Remove pin configuration for UART2 (compared to EA-LPC1788), it is
      not supported by this board.
       * Disable PLL1 and USB clock configuration.
       * The NOR Flash is CFI-compatible, so we do not need to use
      `CONFIG_FLASH_CFI_LEGACY` unlike EA-LPC1788.
       * Update MAC and IP address.
      0b0a296c
  17. 19 Mar, 2012 1 commit
  18. 18 Mar, 2012 2 commits
  19. 20 Feb, 2012 1 commit
  20. 30 Jan, 2012 1 commit
    • Alexander Potashev's avatar
      RT75957. twr-k70f120m: configure the DDR controller for synchronous mode · 514d2c27
      Alexander Potashev authored
      There are 3 ports (port 0, port 1, port 2) between the AHB bus and the
      DDR controller. All of these ports are switched to the synchronous mode
      in this patch.
      
      Any of these 3 ports can work in the synchronous mode only when the
      system clock is sourced from PLL1. Since the DDR clock is also sourced
      from the PLL1 and the CPU clock rate is limited to 120 MHz, we have to
      lower the DDR clock to the same 120 MHz.
      
      The source code is configurable so that you can easily switch back to
      the DDR asynchronous mode:
       * Synchronous mode configuration (see include/configs/twr-k70f120m.h):
          * KINETIS_PLL1_VDIV = 24 (we have to limit DDR clock to 120 MHz)
          * KINETIS_MCGOUT_PLL1 is set (system clock is sourced from PLL1)
          * CONFIG_KINETIS_DDR_SYNC is set
       * Asynchronous mode configuration (see include/configs/twr-k70f120m.h):
          * KINETIS_PLL1_VDIV = 30 (we want the maximum DDR clock: 150 MHz)
          * KINETIS_MCGOUT_PLL1 is not set (system clock is sourced from PLL0)
          * CONFIG_KINETIS_DDR_SYNC is not set
      
      The DDR synchronous mode improves performance: 37.27 BogoMIPS in
      synchronous mode (DDR @ 120 MHz) against 11.03 BogoMIPS in asynchronous
      mode (DDR @ 150 MHz) in Linux.
      514d2c27
  21. 25 Jan, 2012 1 commit
    • Alexander Potashev's avatar
      RT75957. twr-k70f120m: NAND Flash support; environment in flash · 7de399c1
      Alexander Potashev authored
      This patch consists of the following:
      1. NAND Flash Controller (NFC) pin configuration.
      2. NFC clock configuration (enable the clock, initialize the clock rate.)
      3. Changes to the `fsl_nfc` NFC driver:
           * Code cleanup (there were compilation warnings, e.g. unused data
               and functions.)
           * `#include <asm/immap.h>` should not be used on ARM.
           * Disable the GPIO configuration code on ARM.
           * Use `__raw_writel/__raw_readl` instead of `out_be32/in_be32`.
               The registers of the NAND Flash Controller always use the
               same endianness as the MCU core.
           * Make the code in fsl_nfc_get_id() and fsl_nfc_get_status()
               endianness-independent (they were accessing the data from
               32-bit register as an array of u8, this approach is
               endianness-dependent.)
      4. NAND support in the U-Boot configuration file.
      5. Support for environment in the NAND flash in the U-Boot configuration
           file.
      6. Increase the size of the `RAM` memory region to fit the statically
      allocated data for the NAND driver and the U-Boot framework for NAND.
      7de399c1
  22. 19 Jan, 2012 1 commit
  23. 17 Jan, 2012 2 commits
    • Alexander Potashev's avatar
      RT75957. twr-k70f120m: configure DDR memory controller · f9fec77e
      Alexander Potashev authored
      Take the DDR controller configuration (including memory timings) from
      the Freescale's sample code package (KINETIS_120MHZ_SC.zip).
      
      Move `struct kinetis_sim_regs` to
      `include/asm-arm/arch-kinetis/kinetis.h`, because the SIM registers
      have to be updated in order to properly configure the DDR controller for
      the given external memory chip.
      
      DDR works in the asynchronous mode.
      
      Set the DDR clock to 150 MHz (using the PLL1).
      
      For the board with external DDR memory, the DDR configuration code
      should be enabled using the CONFIG_KINETIS_DDR configuration option in
      the U-Boot configuration file.
      f9fec77e
    • Alexander Potashev's avatar
      RT75957. twr-k70f120m: customize the Kinetis port for TWR-K70F120M · 34d45f55
      Alexander Potashev authored
      The `board/freescale/twr-k70f120m/board.c` file was copied from
      `board/freescale/twr-k60n512/board.c` without code changes, because the
      Ethernet pin configuration is compatible on these two boards.
      
      `cpu/arm_cortexm3/kinetis/clock.c` was updated to support the MCG
      (Multipurpose Clock Generator) internal structure on K70 @ 120 MHz
      which is different from the MCG on K60 @ 100 MHz.
      
      The U-Boot configuration file (include/configs/twr-k70f120m.h) was
      copied from the corresponding file for the TWR-K60N512 board and
      customized for the TWR-K70F120M board:
          1. UART pins are different
          2. There is external RAM on the TWR-K70F120M board
          3. The in-MCU flash is 1 MB in size
          4. The clock configuration was updated (120 MHz core clock)
          5. The K70 MCU has 6 GPIO ports (instead of 5 ports on K60)
      34d45f55
  24. 04 Jan, 2012 2 commits
    • Alexander Potashev's avatar
      RT74765. twr-k60n512: reuse the `mcffec` Ethernet driver for TWR-K60N512 · aa4e8b78
      Alexander Potashev authored
      Also add the code for:
      1. Enabling the clock gate for the Ethernet module of the MCU,
      2. Pin configuration for RMII.
      3. Disabling the MPU (the Ethernet module will be unable to work with
           the SRAM otherwise.)
      
      The pull-down resistor for the RXER pin is enabled, because this input
      pin is not connected to the PHY on the TWR-K60N512 board by default.
      aa4e8b78
    • Alexander Potashev's avatar
      RT74765. twr-k60n512: the very basic port · b1277b2a
      Alexander Potashev authored
      Stubs for twr-k60n512 port.
      
      The `.kinetis_flash_conf` section is necessary to keep the MCU flash
      unprotected and allow future flash programming.
      
      This port does not work, because the Watchdog Timer is not unlocked and
      the MCU is reset by WDT shortly after start-up.
      b1277b2a
  25. 02 Dec, 2011 1 commit
  26. 24 Nov, 2011 1 commit
    • Alexander Potashev's avatar
      RT73025. ea-lpc1788: Ethernet driver · 0ee5d6e6
      Alexander Potashev authored
      * The driver structure is almost the same as in the STM32 Ethernet driver.
      * The PHY autodetection code was copied from the STM32 Ethernet driver
          (see `lpc178x_phy_init()`)
      * The speed/duplex detection logic grabbed from the Linux kernel
          (see linux/drivers/net/phy/phy_device.c)
      * The DMA used for Ethernet cannot work with the SoC-internal "System
          RAM", thus we use the external memory (SDRAM) for DMA descriptors
          and buffers.
      0ee5d6e6
  27. 22 Nov, 2011 1 commit
  28. 18 Nov, 2011 2 commits
  29. 14 Nov, 2011 2 commits
  30. 10 Nov, 2011 1 commit
  31. 09 Nov, 2011 1 commit