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Add a new driver named "switch" for run-time selection of wanted devices in DT based on gpios:

    configuration_switch: configuration_switch {
        compatible = "emcraft,configuration-switch";
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_switch>;
    };

...
    pinctrl_switch: switch {
        st,pins {
            /* e5 = 4*16 + 5 = 69 */
            status_pullup = <&gpioe 5 IN
                PULL_UP PUSH_PULL LOW_SPEED>;
        };
    };

...

&usb_fs {
    ...
    configuration-switch-gpios = <&gpioe 5 GPIO_ACTIVE_LOW>;
};

Signed-off-by: Yuri Tikhonov <yur@emcraft.com>

Initial skeleton. U-boot builds but no more porting / testing in this checkin.

Initial skeleton of the STM32F7 SOM port. The configuration builds
but hasn't been yet tried on the target.

The port tested on the Emcraft STM32F4 SOM Rev 1A.

 make stm-som_config - for 2A
 make stm-som-1a_config - for 1A

configurations for 2A ("m2s-som_config") and 1A ("m2-som-1a_config").

changes in that tharget, thus it is supported in a separate configuration file
and the board-specific directory.

as that stm-som_config builds cleanly.

to the U-Boot prompt on the serial console.

modules running at 120 and 150 MHz.

Supported:
 - UART0 (57600)
 - SPI0 (non-DMA)
 - Ethernet
 - LPDDR
 - Env in SPI Flash

U-boot to run from eNVM at offset 0x20000:

- to program that U-boot to eNVM: cptf 0x20000 ${loadaddr} ${filesize} 0
- to run that U-boot from eNVM: go 20375

 * Add Makefile target `lpc1850-eval_config`.
 * Set the system prompt to `LPC1850-EVAL> `.
 * Change CONFIG_MEM_NVM_LEN from 128 KBytes to 96 KBytes to match the
size of the largest continuous region of internal SRAM on LPC1850.
 * Adjust clock configuration for the 180MHz maximum core clock rate on
LPC1850: set the PLL1 multiplier value to 15.
 * Adjust SDRAM timings for the 180MHz maximum core clock rate on
LPC1850.
 * Adjust NOR flash timings for the 180MHz maximum core clock rate on
LPC1850.
 * Change default MAC address and IP address of the board defined in the
U-Boot environment.

 * This 16-byte header is required to boot U-Boot to the Hitex LPC4350 Eval
board over USB0. The same header is required to make the Boot ROM
bootloader boot images larger than 16KBytes from NOR flash.
 * The header will be automatically added to `u-boot.bin` if
CONFIG_LPC18XX_BOOTHEADER is enabled in the U-Boot configuration.

Support the following features:
 * Serial console on USART0.
 * Common pin configuration functions (needed for USART0).
 * Clock configuration: The Cortex-M4 core runs at 204 MHz.
 * `cptf` command is technically available, but has no effect since there is no
internal flash on LPC18x0/LPC43x0 MCUs.
 * The lowest SRAM region (128 KB at 0x10000000) is reserved for the currently
running U-Boot image.

 * Add Makefile target `k70-som_config`.
 * Start K70-SOM board support code by cloning off the TWR-K70F120M
board-specific code.
 * Update DDR controller configuration to interact with the LPDDR memory chip.
Update timings for a 120 MHz DDR clock.
 * Remove configuration of pins NFC_D8..NFC_D15, they are not used by 8-bit NAND
flashes.
 * Optionally support 8-bit NAND flashes in the `fsl_nfc.c` driver.
 * Set correct size of RAM (64 MB).
 * Do not configure the LCD clock, because we do not support LCDs with K70-SOM
yet.
 * Update U-Boot prompt, IP address, MAC address, bootargs, hostname.

 * Add Makefile target `lpc-lnx-evb_config`.
 * Configure one more EMC address pin on LPC-LNX-EVB (in comparison to
EA-LPC1788) to make all 16 MBytes of NOR Flash work.
 * Remove pin configuration for UART2 (compared to EA-LPC1788), it is
not supported by this board.
 * Disable PLL1 and USB clock configuration.
 * The NOR Flash is CFI-compatible, so we do not need to use
`CONFIG_FLASH_CFI_LEGACY` unlike EA-LPC1788.
 * Update MAC and IP address.

At this point, U-boot just builds. No validation on the target was
performed so far.

Tested by loading it onto STM32F2 and making sure that it shows the right
prompt and other cosmetic messages.

The `board/freescale/twr-k70f120m/board.c` file was copied from
`board/freescale/twr-k60n512/board.c` without code changes, because the
Ethernet pin configuration is compatible on these two boards.

`cpu/arm_cortexm3/kinetis/clock.c` was updated to support the MCG
(Multipurpose Clock Generator) internal structure on K70 @ 120 MHz
which is different from the MCG on K60 @ 100 MHz.

The U-Boot configuration file (include/configs/twr-k70f120m.h) was
copied from the corresponding file for the TWR-K60N512 board and
customized for the TWR-K70F120M board:
    1. UART pins are different
    2. There is external RAM on the TWR-K70F120M board
    3. The in-MCU flash is 1 MB in size
    4. The clock configuration was updated (120 MHz core clock)
    5. The K70 MCU has 6 GPIO ports (instead of 5 ports on K60)

Stubs for twr-k60n512 port.

The `.kinetis_flash_conf` section is necessary to keep the MCU flash
unprotected and allow future flash programming.

This port does not work, because the Watchdog Timer is not unlocked and
the MCU is reset by WDT shortly after start-up.

u-boot-lpc.bin.

For EA-LPC1788, the U-Boot image suitable for programming is u-boot-lpc.bin.
This is inconsistent with other supported targets, where the image is
u-boot.bin. This patch fixes this.

The checksum at predefined offset is required for execution of images
from the LPC178X eNVM. This patch automates the creation of this
checksum, the resulted images are u-boot-lpc.bin and u-boot-lpc.hex.

Stubs for ea-lpc1788 port.

There's no so much differences between different families of STM32.
Manual (migrate STM32F1 -> STM32F2) says, that GPIO and Flash are
significantly different, the other interfaces (we use) are almost
the same. So, let's name this arch as 'stm32', not 'stm32f2' (as we
do this in linux).
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>

Stubs for stm3220g-eval port.
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>

These are the preparations for support for another Cortex-M3 based
processor, STM32F2.
Signed-off-by: Yuri Tikhonov <yur@emcraft.com>

Tested that it builds but didn't boot the new configuration on
the board yet.

This commit removes support for the Actel F2 board (as well as
any references to this board in the code).

Added A2F-LNX-EVB board support, based on "actel_f2".
Supported:
	Clocks, external RAM (8MB), UART, Flash (16MB).
Unsupported:
	Network