1. 03 Mar, 2017 1 commit
    • Sergei Miroshnichenko's avatar
      RM#1313 fdt: stm32: switch: Add run-time gpio-based status switching of DT nodes. · 74ebeb68
      Sergei Miroshnichenko authored
      Add a new driver named "switch" for run-time selection of wanted devices in DT based on gpios:
      
          configuration_switch: configuration_switch {
              compatible = "emcraft,configuration-switch";
              pinctrl-names = "default";
              pinctrl-0 = <&pinctrl_switch>;
          };
      
      ...
          pinctrl_switch: switch {
              st,pins {
                  /* e5 = 4*16 + 5 = 69 */
                  status_pullup = <&gpioe 5 IN
                      PULL_UP PUSH_PULL LOW_SPEED>;
              };
          };
      
      ...
      
      &usb_fs {
          ...
          configuration-switch-gpios = <&gpioe 5 GPIO_ACTIVE_LOW>;
      };
      74ebeb68
  2. 16 Dec, 2016 1 commit
  3. 24 Oct, 2016 1 commit
  4. 26 Oct, 2015 1 commit
  5. 20 Apr, 2015 1 commit
  6. 10 Jan, 2015 1 commit
  7. 23 Apr, 2014 1 commit
  8. 05 Dec, 2013 1 commit
  9. 18 Nov, 2013 1 commit
  10. 21 Oct, 2013 1 commit
  11. 10 Oct, 2013 1 commit
  12. 05 Jul, 2013 1 commit
  13. 03 Jul, 2013 1 commit
  14. 18 Apr, 2013 1 commit
  15. 05 Apr, 2013 1 commit
  16. 29 Jan, 2013 1 commit
  17. 03 Dec, 2012 1 commit
  18. 20 Nov, 2012 1 commit
  19. 02 Nov, 2012 1 commit
  20. 13 Jun, 2012 1 commit
  21. 23 May, 2012 1 commit
    • Alexander Potashev's avatar
      RT78427. lpc1850-eval: Add support for Hitex LPC1850 Eval board · 40aa1110
      Alexander Potashev authored
       * Add Makefile target `lpc1850-eval_config`.
       * Set the system prompt to `LPC1850-EVAL> `.
       * Change CONFIG_MEM_NVM_LEN from 128 KBytes to 96 KBytes to match the
      size of the largest continuous region of internal SRAM on LPC1850.
       * Adjust clock configuration for the 180MHz maximum core clock rate on
      LPC1850: set the PLL1 multiplier value to 15.
       * Adjust SDRAM timings for the 180MHz maximum core clock rate on
      LPC1850.
       * Adjust NOR flash timings for the 180MHz maximum core clock rate on
      LPC1850.
       * Change default MAC address and IP address of the board defined in the
      U-Boot environment.
      40aa1110
  22. 04 May, 2012 1 commit
    • Alexander Potashev's avatar
      RT77744. lpc4350-eval: Add header to the U-Boot image · 74cfefd6
      Alexander Potashev authored
       * This 16-byte header is required to boot U-Boot to the Hitex LPC4350 Eval
      board over USB0. The same header is required to make the Boot ROM
      bootloader boot images larger than 16KBytes from NOR flash.
       * The header will be automatically added to `u-boot.bin` if
      CONFIG_LPC18XX_BOOTHEADER is enabled in the U-Boot configuration.
      74cfefd6
  23. 24 Apr, 2012 1 commit
    • Alexander Potashev's avatar
      RT77744. lpc4350-eval: Basic port · 55246688
      Alexander Potashev authored
      Support the following features:
       * Serial console on USART0.
       * Common pin configuration functions (needed for USART0).
       * Clock configuration: The Cortex-M4 core runs at 204 MHz.
       * `cptf` command is technically available, but has no effect since there is no
      internal flash on LPC18x0/LPC43x0 MCUs.
       * The lowest SRAM region (128 KB at 0x10000000) is reserved for the currently
      running U-Boot image.
      55246688
  24. 11 Apr, 2012 1 commit
    • Alexander Potashev's avatar
      RT77788. k70-som: Add support for the Emcraft K70-SOM + SOM-BSB platform · 065d7e55
      Alexander Potashev authored
       * Add Makefile target `k70-som_config`.
       * Start K70-SOM board support code by cloning off the TWR-K70F120M
      board-specific code.
       * Update DDR controller configuration to interact with the LPDDR memory chip.
      Update timings for a 120 MHz DDR clock.
       * Remove configuration of pins NFC_D8..NFC_D15, they are not used by 8-bit NAND
      flashes.
       * Optionally support 8-bit NAND flashes in the `fsl_nfc.c` driver.
       * Set correct size of RAM (64 MB).
       * Do not configure the LCD clock, because we do not support LCDs with K70-SOM
      yet.
       * Update U-Boot prompt, IP address, MAC address, bootargs, hostname.
      065d7e55
  25. 29 Mar, 2012 1 commit
    • Alexander Potashev's avatar
      RT77452. Add support for Emcraft's LPC-LNX-EVB board · 0b0a296c
      Alexander Potashev authored
       * Add Makefile target `lpc-lnx-evb_config`.
       * Configure one more EMC address pin on LPC-LNX-EVB (in comparison to
      EA-LPC1788) to make all 16 MBytes of NOR Flash work.
       * Remove pin configuration for UART2 (compared to EA-LPC1788), it is
      not supported by this board.
       * Disable PLL1 and USB clock configuration.
       * The NOR Flash is CFI-compatible, so we do not need to use
      `CONFIG_FLASH_CFI_LEGACY` unlike EA-LPC1788.
       * Update MAC and IP address.
      0b0a296c
  26. 18 Mar, 2012 1 commit
  27. 19 Jan, 2012 1 commit
  28. 17 Jan, 2012 1 commit
    • Alexander Potashev's avatar
      RT75957. twr-k70f120m: customize the Kinetis port for TWR-K70F120M · 34d45f55
      Alexander Potashev authored
      The `board/freescale/twr-k70f120m/board.c` file was copied from
      `board/freescale/twr-k60n512/board.c` without code changes, because the
      Ethernet pin configuration is compatible on these two boards.
      
      `cpu/arm_cortexm3/kinetis/clock.c` was updated to support the MCG
      (Multipurpose Clock Generator) internal structure on K70 @ 120 MHz
      which is different from the MCG on K60 @ 100 MHz.
      
      The U-Boot configuration file (include/configs/twr-k70f120m.h) was
      copied from the corresponding file for the TWR-K60N512 board and
      customized for the TWR-K70F120M board:
          1. UART pins are different
          2. There is external RAM on the TWR-K70F120M board
          3. The in-MCU flash is 1 MB in size
          4. The clock configuration was updated (120 MHz core clock)
          5. The K70 MCU has 6 GPIO ports (instead of 5 ports on K60)
      34d45f55
  29. 04 Jan, 2012 1 commit
    • Alexander Potashev's avatar
      RT74765. twr-k60n512: the very basic port · b1277b2a
      Alexander Potashev authored
      Stubs for twr-k60n512 port.
      
      The `.kinetis_flash_conf` section is necessary to keep the MCU flash
      unprotected and allow future flash programming.
      
      This port does not work, because the Watchdog Timer is not unlocked and
      the MCU is reset by WDT shortly after start-up.
      b1277b2a
  30. 06 Dec, 2011 1 commit
  31. 25 Nov, 2011 1 commit
  32. 08 Nov, 2011 1 commit
  33. 07 Oct, 2011 1 commit
    • Yuri Tikhonov's avatar
      RT72064. stm32f2: rename to stm32 · e1616ea3
      Yuri Tikhonov authored
      There's no so much differences between different families of STM32.
      Manual (migrate STM32F1 -> STM32F2) says, that GPIO and Flash are
      significantly different, the other interfaces (we use) are almost
      the same. So, let's name this arch as 'stm32', not 'stm32f2' (as we
      do this in linux).
      Signed-off-by: default avatarYuri Tikhonov <yur@emcraft.com>
      e1616ea3
  34. 17 Sep, 2011 2 commits
  35. 09 Jul, 2011 1 commit
  36. 02 Jun, 2011 1 commit
  37. 09 Nov, 2010 1 commit
  38. 19 Oct, 2010 1 commit
    • Sergei Poselenov's avatar
      RT #61653 · 203013c8
      Sergei Poselenov authored
      Added A2F-LNX-EVB board support, based on "actel_f2".
      Supported:
      	Clocks, external RAM (8MB), UART, Flash (16MB).
      Unsupported:
      	Network
      203013c8
  39. 31 Aug, 2010 1 commit