- 17 Jan, 2012 2 commits
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Alexander Potashev authored
Take the DDR controller configuration (including memory timings) from the Freescale's sample code package (KINETIS_120MHZ_SC.zip). Move `struct kinetis_sim_regs` to `include/asm-arm/arch-kinetis/kinetis.h`, because the SIM registers have to be updated in order to properly configure the DDR controller for the given external memory chip. DDR works in the asynchronous mode. Set the DDR clock to 150 MHz (using the PLL1). For the board with external DDR memory, the DDR configuration code should be enabled using the CONFIG_KINETIS_DDR configuration option in the U-Boot configuration file.
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Alexander Potashev authored
The `board/freescale/twr-k70f120m/board.c` file was copied from `board/freescale/twr-k60n512/board.c` without code changes, because the Ethernet pin configuration is compatible on these two boards. `cpu/arm_cortexm3/kinetis/clock.c` was updated to support the MCG (Multipurpose Clock Generator) internal structure on K70 @ 120 MHz which is different from the MCG on K60 @ 100 MHz. The U-Boot configuration file (include/configs/twr-k70f120m.h) was copied from the corresponding file for the TWR-K60N512 board and customized for the TWR-K70F120M board: 1. UART pins are different 2. There is external RAM on the TWR-K70F120M board 3. The in-MCU flash is 1 MB in size 4. The clock configuration was updated (120 MHz core clock) 5. The K70 MCU has 6 GPIO ports (instead of 5 ports on K60)
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- 16 Jan, 2012 1 commit
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Alexander Potashev authored
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- 11 Jan, 2012 1 commit
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Sergei Poselenov authored
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- 06 Jan, 2012 1 commit
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Sergei Poselenov authored
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- 04 Jan, 2012 12 commits
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Alexander Potashev authored
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Alexander Potashev authored
Self-upgrade is possible now: tftp 0x1fff5800 aspotashev/k60/u-boot.bin cptf 0 ${fileaddr} ${filesize} 1 Since there is no external RAM on the TWR-K60N512 board, we put the new U-Boot image into SRAM. The address of the RAM_BUF region (0x1fff5800 in the above example) can be checked in the `u-boot.map` file. The RAM_BUF region is currently 84 Kbytes in size. U-Boot images larger than this size cannot be safely loaded.
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Alexander Potashev authored
Write the necessary data into flash by flash sectors (2 Kbytes). Use the "Program Section" command to write a complete flash sector. If only a part of the sector should be updated, firstly load the existing data that should not be changed into the write buffer (flash programming acceleration RAM), and then write from this buffer into the flash sector. This technique makes it possible to update even single bytes without damaging other data in the same flash sector. Before writing at the flash address 0x40C, a check is performed to make sure the MCU will not switch to the secure state. All functions that may be called from `envm_write()` are put into the `.ramcode` section, because the internal flash is not a safe place when self-upgrade is in progress. Like in the FNET project, we disable Single Entry Buffer and Data Cache via FMC registers. This must be a workaround for an errata.
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Alexander Potashev authored
Also add the code for: 1. Enabling the clock gate for the Ethernet module of the MCU, 2. Pin configuration for RMII. 3. Disabling the MPU (the Ethernet module will be unable to work with the SRAM otherwise.) The pull-down resistor for the RXER pin is enabled, because this input pin is not connected to the PHY on the TWR-K60N512 board by default.
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Alexander Potashev authored
The value for the RCR (Receive Control Register) was wrong in the half-duplex mode. The `mcf*` targets were not checked for clean build.
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Alexander Potashev authored
The `mcf*` targets were not checked for clean build.
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Alexander Potashev authored
Also in this commit: 1. `kinetis_periph_enable()` for enabling clocks on various MCU modules. 2. Minimal GPIO driver with the `kinetis_gpio_config()` function. FIFOs are not implemented in this driver (they can be enables via the PFIFO, TXWATER and RXWATER registers), because on K60 only UART0 has a more than single-dataword FIFO, and UART0 is not used on the TWR-K60N512 board. We use the UART3 on the TWR-K60N512 board which is connected to the DB-9 port on the TWR-SER board in the TWR-K60N512-KIT board set.
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Alexander Potashev authored
Core/system clock rate: 100 MHz Peripheral clock rate: 50 MHz FlexBus clock rate: 50 MHz Flash clock rate: 25 MHz The PLL takes the 50 MHz on-board external clock from the EXTAL pin and feeds the MCGOUTCLK with a 100 MHz clock. On the Kinetis MCU, we have to sequentally switch between 3 clocking modes until we can enter the desired PEE mode (PLL Engaged External mode). The `KINETIS_MCG_C2_EREFS_MSK` and `KINETIS_MCG_C2_HGO_MSK` bits should be cleared, otherwise the Ethernet module of the MCU cannot send nor receive packets. Testing: `udelay(1000)` works correctly (tested by blinking the green LED.)
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Alexander Potashev authored
If we do not disable the watchdog timer in a few MCU clocks after reset, it will reset the MCU.
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Alexander Potashev authored
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Alexander Potashev authored
* The USB clock configuration code is disabled by default * PLL1 will be configured only if the USB clock is enabled by defining the CONFIG_LPC178X_USB_DIV option in the board configuration file.
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Alexander Potashev authored
Stubs for twr-k60n512 port. The `.kinetis_flash_conf` section is necessary to keep the MCU flash unprotected and allow future flash programming. This port does not work, because the Watchdog Timer is not unlocked and the MCU is reset by WDT shortly after start-up.
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- 25 Dec, 2011 1 commit
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Sergei Poselenov authored
WheN left in "addip", this results in the boards hangup, see #76050.
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- 14 Dec, 2011 1 commit
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Alexander Potashev authored
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- 07 Dec, 2011 1 commit
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Alexander Potashev authored
Hang-up scenario before this patch: At the time `udelay()` is called, the current value in the SYSTICK timer (`systick->val`) may be very close to, but greater than the number of clocks left to tick (`clc`). Since `systick->val` is greater than `clc`, we use the `while` loop from the `else` block. But this `while` loops only checks that `systick->val` is greater than `(tmp - clc)` which is a very small positive integer (because `tmp` is very close to `clc`.) The `while` loop will now terminate only if we manage to catch `systick->val` in a very thin range between 0 and `(tmp - clc)`. The comparison inside the `while` loop condition takes a considerable number of CPU clocks, that makes it hard to find `systick->val` between 0 and `(tmp - clc)`, we just step over this small range. This bug manifested when erasing NOR flash on EA-LPC1788-32: the `udelay(1)` call in `flash_status_check()` in `drivers/mtd/cfi_flash.c` was hanging.
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- 06 Dec, 2011 3 commits
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Sergei Poselenov authored
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Sergei Poselenov authored
u-boot-lpc.bin. For EA-LPC1788, the U-Boot image suitable for programming is u-boot-lpc.bin. This is inconsistent with other supported targets, where the image is u-boot.bin. This patch fixes this.
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Alexander Potashev authored
To avoid hang-up of the Ethernet block after Cortex-M3 software reset (SYSRESET), we need to reset the Ethernet PHY immediately before performing the SYSRESET. All new code added in this patch should be in placed in `.ramcode`, because we might want to do a software reset after self-upgrade. Since we cannot use `printf()` in functions that may be called during self-upgrade (`printf()` is too big for `.ramcode`), the `lpc178x_phy_init()` function cannot be easily used in `lpc178x_phy_final_reset()`. Because of this, we use a pre-set PHY address (`CONFIG_LPC178X_ETH_PHY_ADDR`) instead of doing automatic PHY discovery that is usually done in `lpc178x_phy_init()`. If Ethernet is not enabled in the U-Boot configuration file, we do not perform the PHY reset. This leads to a minor bug: if you install U-Boot without Ethernet support into your board and do a self-upgrade to another build of U-Boot with Ethernet support, the Ethernet driver will hang in the latter U-Boot unless you have done a full reset (by pushing the SW1 button) after self-upgrade.
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- 02 Dec, 2011 4 commits
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Alexander Potashev authored
Pass "mem=16M" parameter to the Linux kernel on the boards `ea-lpc1788` and `stm3220g-eval`.
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Sergei Poselenov authored
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Sergei Poselenov authored
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Sergei Poselenov authored
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- 01 Dec, 2011 2 commits
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Alexander Potashev authored
Put multiline `printf()` calls in curly braces.
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Alexander Potashev authored
We use IAP commands for writing into eNVM. All code and pre-initialized data that are used during self-upgrade are forced to reside in `.ramcode` and `.data` respectively. Uninitialized data go into `.bss` automatically.
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- 30 Nov, 2011 1 commit
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Alexander Potashev authored
1. Fixed the algorithm for checking if the transmit buffers are full. 2. Removed unnecessary `udelay()` calls that were kept after copying the code from the LPCware's U-Boot port. 3. Increased the numbers of receive and transmit DMA buffers.
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- 25 Nov, 2011 3 commits
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Sergei Poselenov authored
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Alexander Potashev authored
UART0 has id=0 in Linux.
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Sergei Poselenov authored
The checksum at predefined offset is required for execution of images from the LPC178X eNVM. This patch automates the creation of this checksum, the resulted images are u-boot-lpc.bin and u-boot-lpc.hex.
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- 24 Nov, 2011 4 commits
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Alexander Potashev authored
This is required for any code execution (including the Linux kernel) in the external RAM on LPC178x/7x.
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Alexander Potashev authored
* The driver structure is almost the same as in the STM32 Ethernet driver. * The PHY autodetection code was copied from the STM32 Ethernet driver (see `lpc178x_phy_init()`) * The speed/duplex detection logic grabbed from the Linux kernel (see linux/drivers/net/phy/phy_device.c) * The DMA used for Ethernet cannot work with the SoC-internal "System RAM", thus we use the external memory (SDRAM) for DMA descriptors and buffers.
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Alexander Potashev authored
* ..._BIT definitions used for single bits converted to ..._MSK definitions to remove extra (1 << ...something...) expressions from the code. * Added more definitions of bits that are necessary for the Linux kernel port.
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Alexander Potashev authored
Convert `struct lpc178x_scc_regs` to the STM32/SmartFusion structure style, i.e. use `rsvN[M]` hole fillers instead of `union`s for alignment.
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- 22 Nov, 2011 1 commit
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Alexander Potashev authored
The DRAM configuration is the same as in the existing port from LPCware.
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- 18 Nov, 2011 2 commits
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Alexander Potashev authored
Make clear that `CONFIG_SYS_BOARD_REV_STR` is the revision number.
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Sergei Poselenov authored
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