1. 28 Feb, 2012 1 commit
    • Alexander Potashev's avatar
      RT77090. kinetis eth: Fix receiving of Ethernet packets · fe65e8bf
      Alexander Potashev authored
      The Ethernet module of the MCU requires that the RDAR register is set
      only after a while after the RDSR register is set; i.e. the RDAR
      register should not be set immediately after RDSR during initialization
      of the Ethernet module.
        1. If we write to the ENET_RDAR register immediately after initializing
      the ENET_RDSR register, the incoming packets can _never_ be received.
        2. If we make the MCU wait for 10us before writing to ENET_RDAR, the
      incoming packets are _always_ received correctly.
        3. If we perform a few instructions (about 10 of them) between setting
      RDSR and RDAR, then the problem manifests randomly from time to time.
      
      In order to fix the bug, we add a 10us delay just before writing
      to the RDAR register.
      
      Things just work in Freescale MQX and in Linux, because there is a lot
      of other initialization code between the RDAR and RDSR register are set,
      so this other initialization code serves as a delay.
      fe65e8bf
  2. 22 Feb, 2012 1 commit
  3. 20 Feb, 2012 1 commit
  4. 10 Feb, 2012 1 commit
    • Alexander Potashev's avatar
      RT76453. twr-k70f120m: make env bad block tolerant · 65d91d4f
      Alexander Potashev authored
       * Use `CONFIG_ENV_RANGE` to let U-Boot use any of the first 4 blocks of the
      NAND flash for storage of the U-Boot environment.
       * Use `CONFIG_ENV_OFFSET_REDUND`: if the block where the main copy of the U-Boot
      environment resides becomes bad, the environment will be restored from the
      redundant copy. Allocate another 4 blocks for the redundant copy of the
      environment.
       * Update the `flashaddr` variable and the `update` macro in the U-Boot
      environment.
       * Increase the size of the malloc() pool, needed to use both
      the `CONFIG_ENV_RANGE` and the `CONFIG_ENV_[...]_REDUND` features.
      65d91d4f
  5. 04 Feb, 2012 1 commit
  6. 31 Jan, 2012 1 commit
  7. 30 Jan, 2012 2 commits
    • Alexander Potashev's avatar
      RT75957. twr-k70f120m: configure the DDR controller for synchronous mode · 514d2c27
      Alexander Potashev authored
      There are 3 ports (port 0, port 1, port 2) between the AHB bus and the
      DDR controller. All of these ports are switched to the synchronous mode
      in this patch.
      
      Any of these 3 ports can work in the synchronous mode only when the
      system clock is sourced from PLL1. Since the DDR clock is also sourced
      from the PLL1 and the CPU clock rate is limited to 120 MHz, we have to
      lower the DDR clock to the same 120 MHz.
      
      The source code is configurable so that you can easily switch back to
      the DDR asynchronous mode:
       * Synchronous mode configuration (see include/configs/twr-k70f120m.h):
          * KINETIS_PLL1_VDIV = 24 (we have to limit DDR clock to 120 MHz)
          * KINETIS_MCGOUT_PLL1 is set (system clock is sourced from PLL1)
          * CONFIG_KINETIS_DDR_SYNC is set
       * Asynchronous mode configuration (see include/configs/twr-k70f120m.h):
          * KINETIS_PLL1_VDIV = 30 (we want the maximum DDR clock: 150 MHz)
          * KINETIS_MCGOUT_PLL1 is not set (system clock is sourced from PLL0)
          * CONFIG_KINETIS_DDR_SYNC is not set
      
      The DDR synchronous mode improves performance: 37.27 BogoMIPS in
      synchronous mode (DDR @ 120 MHz) against 11.03 BogoMIPS in asynchronous
      mode (DDR @ 150 MHz) in Linux.
      514d2c27
    • Alexander Potashev's avatar
      RT74765, RT75957. twr-k60n512, twr-k70f120m: lower Ethernet link up/Tx timeout · 75b99c96
      Alexander Potashev authored
      Lower the Link UP and Ethernet transmit timeout to about 2 seconds.
      75b99c96
  8. 25 Jan, 2012 6 commits
  9. 20 Jan, 2012 2 commits
  10. 19 Jan, 2012 1 commit
  11. 17 Jan, 2012 2 commits
    • Alexander Potashev's avatar
      RT75957. twr-k70f120m: configure DDR memory controller · f9fec77e
      Alexander Potashev authored
      Take the DDR controller configuration (including memory timings) from
      the Freescale's sample code package (KINETIS_120MHZ_SC.zip).
      
      Move `struct kinetis_sim_regs` to
      `include/asm-arm/arch-kinetis/kinetis.h`, because the SIM registers
      have to be updated in order to properly configure the DDR controller for
      the given external memory chip.
      
      DDR works in the asynchronous mode.
      
      Set the DDR clock to 150 MHz (using the PLL1).
      
      For the board with external DDR memory, the DDR configuration code
      should be enabled using the CONFIG_KINETIS_DDR configuration option in
      the U-Boot configuration file.
      f9fec77e
    • Alexander Potashev's avatar
      RT75957. twr-k70f120m: customize the Kinetis port for TWR-K70F120M · 34d45f55
      Alexander Potashev authored
      The `board/freescale/twr-k70f120m/board.c` file was copied from
      `board/freescale/twr-k60n512/board.c` without code changes, because the
      Ethernet pin configuration is compatible on these two boards.
      
      `cpu/arm_cortexm3/kinetis/clock.c` was updated to support the MCG
      (Multipurpose Clock Generator) internal structure on K70 @ 120 MHz
      which is different from the MCG on K60 @ 100 MHz.
      
      The U-Boot configuration file (include/configs/twr-k70f120m.h) was
      copied from the corresponding file for the TWR-K60N512 board and
      customized for the TWR-K70F120M board:
          1. UART pins are different
          2. There is external RAM on the TWR-K70F120M board
          3. The in-MCU flash is 1 MB in size
          4. The clock configuration was updated (120 MHz core clock)
          5. The K70 MCU has 6 GPIO ports (instead of 5 ports on K60)
      34d45f55
  12. 16 Jan, 2012 1 commit
  13. 11 Jan, 2012 1 commit
  14. 06 Jan, 2012 1 commit
  15. 04 Jan, 2012 12 commits
    • Alexander Potashev's avatar
    • Alexander Potashev's avatar
      RT74765. twr-k60n512: expand RAM_BUF to put u-boot.bin images there · 104358b0
      Alexander Potashev authored
      Self-upgrade is possible now:
      	tftp 0x1fff5800 aspotashev/k60/u-boot.bin
      	cptf 0 ${fileaddr} ${filesize} 1
      
      Since there is no external RAM on the TWR-K60N512 board, we put
      the new U-Boot image into SRAM. The address of the RAM_BUF region
      (0x1fff5800 in the above example) can be checked in the `u-boot.map`
      file.
      
      The RAM_BUF region is currently 84 Kbytes in size. U-Boot images larger
      than this size cannot be safely loaded.
      104358b0
    • Alexander Potashev's avatar
      RT74765. twr-k60n512: implement `envm_write()` for the `cptf` command · 4e324723
      Alexander Potashev authored
      Write the necessary data into flash by flash sectors (2 Kbytes).
      Use the "Program Section" command to write a complete flash sector.
      
      If only a part of the sector should be updated, firstly load the
      existing data that should not be changed into the write buffer (flash
      programming acceleration RAM), and then write from this buffer into the
      flash sector.
      This technique makes it possible to update even single bytes without
      damaging other data in the same flash sector.
      
      Before writing at the flash address 0x40C, a check is performed to make
      sure the MCU will not switch to the secure state.
      
      All functions that may be called from `envm_write()` are put into the
      `.ramcode` section, because the internal flash is not a safe place
      when self-upgrade is in progress.
      
      Like in the FNET project, we disable Single Entry Buffer and Data Cache
      via FMC registers. This must be a workaround for an errata.
      4e324723
    • Alexander Potashev's avatar
      RT74765. twr-k60n512: reuse the `mcffec` Ethernet driver for TWR-K60N512 · aa4e8b78
      Alexander Potashev authored
      Also add the code for:
      1. Enabling the clock gate for the Ethernet module of the MCU,
      2. Pin configuration for RMII.
      3. Disabling the MPU (the Ethernet module will be unable to work with
           the SRAM otherwise.)
      
      The pull-down resistor for the RXER pin is enabled, because this input
      pin is not connected to the PHY on the TWR-K60N512 board by default.
      aa4e8b78
    • Alexander Potashev's avatar
      RT74765. twr-k60n512: Fix a bug; increase configurability of `mcffec` · e066e32e
      Alexander Potashev authored
      The value for the RCR (Receive Control Register) was wrong in the
      half-duplex mode.
      
      The `mcf*` targets were not checked for clean build.
      e066e32e
    • Alexander Potashev's avatar
      RT74765. twr-k60n512: Untie the `mcffec` driver from m68k · 8bd96b7b
      Alexander Potashev authored
      The `mcf*` targets were not checked for clean build.
      8bd96b7b
    • Alexander Potashev's avatar
      RT74765. twr-k60n512: serial driver implementation · 7e83dab7
      Alexander Potashev authored
      Also in this commit:
      1. `kinetis_periph_enable()` for enabling clocks on various MCU modules.
      2. Minimal GPIO driver with the `kinetis_gpio_config()` function.
      
      FIFOs are not implemented in this driver (they can be enables via the
      PFIFO, TXWATER and RXWATER registers), because on K60 only UART0
      has a more than single-dataword FIFO, and UART0 is not used on the
      TWR-K60N512 board.
      
      We use the UART3 on the TWR-K60N512 board which is connected to the DB-9
      port on the TWR-SER board in the TWR-K60N512-KIT board set.
      7e83dab7
    • Alexander Potashev's avatar
      RT74765. twr-k60n512: setup clocks · 5c122449
      Alexander Potashev authored
      Core/system clock rate: 100 MHz
      Peripheral clock rate:   50 MHz
      FlexBus clock rate:      50 MHz
      Flash clock rate:        25 MHz
      
      The PLL takes the 50 MHz on-board external clock from the EXTAL pin and
      feeds the MCGOUTCLK with a 100 MHz clock.
      
      On the Kinetis MCU, we have to sequentally switch between 3 clocking
      modes until we can enter the desired PEE mode (PLL Engaged External
      mode).
      
      The `KINETIS_MCG_C2_EREFS_MSK` and `KINETIS_MCG_C2_HGO_MSK` bits should
      be cleared, otherwise the Ethernet module of the MCU cannot send nor
      receive packets.
      
      Testing:
          `udelay(1000)` works correctly (tested by blinking the green LED.)
      5c122449
    • Alexander Potashev's avatar
      RT74765. twr-k60n512: disable the watchdog, it is enabled on reset · 5d52a173
      Alexander Potashev authored
      If we do not disable the watchdog timer in a few MCU clocks after reset,
      it will reset the MCU.
      5d52a173
    • Alexander Potashev's avatar
      b7cb4c3a
    • Alexander Potashev's avatar
      RT75747. ea-lpc1788: USB clock configuration · 72e40b68
      Alexander Potashev authored
      * The USB clock configuration code is disabled by default
      * PLL1 will be configured only if the USB clock is enabled by defining
          the CONFIG_LPC178X_USB_DIV option in the board configuration file.
      72e40b68
    • Alexander Potashev's avatar
      RT74765. twr-k60n512: the very basic port · b1277b2a
      Alexander Potashev authored
      Stubs for twr-k60n512 port.
      
      The `.kinetis_flash_conf` section is necessary to keep the MCU flash
      unprotected and allow future flash programming.
      
      This port does not work, because the Watchdog Timer is not unlocked and
      the MCU is reset by WDT shortly after start-up.
      b1277b2a
  16. 25 Dec, 2011 1 commit
  17. 14 Dec, 2011 1 commit
  18. 07 Dec, 2011 1 commit
    • Alexander Potashev's avatar
      RT73025. ea-lpc1788: fix hang-up in `udelay()` for all Cortex-M3 targets · a53bb5ce
      Alexander Potashev authored
      Hang-up scenario before this patch:
      At the time `udelay()` is called, the current value in
          the SYSTICK timer (`systick->val`) may be very close to, but greater
          than the number of clocks left to tick (`clc`).
      Since `systick->val` is greater than `clc`, we use the `while` loop from
          the `else` block. But this `while` loops only checks that `systick->val`
          is greater than `(tmp - clc)` which is a very small positive integer
          (because `tmp` is very close to `clc`.) The `while` loop will now
          terminate only if we manage to catch `systick->val` in a very thin
          range between 0 and `(tmp - clc)`. The comparison inside the `while`
          loop condition takes a considerable number of CPU clocks, that makes it
          hard to find `systick->val` between 0 and `(tmp - clc)`, we just step
          over this small range.
      
      This bug manifested when erasing NOR flash on EA-LPC1788-32: the
      `udelay(1)` call in `flash_status_check()` in `drivers/mtd/cfi_flash.c`
      was hanging.
      a53bb5ce
  19. 06 Dec, 2011 3 commits
    • Sergei Poselenov's avatar
    • Sergei Poselenov's avatar
      RT #73025. ea-lpc1788: create u-boot.bin with checksum instead of · d6962b42
      Sergei Poselenov authored
      u-boot-lpc.bin.
      
      For EA-LPC1788, the U-Boot image suitable for programming is u-boot-lpc.bin.
      This is inconsistent with other supported targets, where the image is
      u-boot.bin. This patch fixes this.
      d6962b42
    • Alexander Potashev's avatar
      RT73025. ea-lpc1788: fix hang-up in Ethernet driver after SYSRESET · 6c05ceb4
      Alexander Potashev authored
      To avoid hang-up of the Ethernet block after Cortex-M3 software reset
      (SYSRESET), we need to reset the Ethernet PHY immediately before
      performing the SYSRESET.
      
      All new code added in this patch should be in placed in `.ramcode`,
      because we might want to do a software reset after self-upgrade.
      
      Since we cannot use `printf()` in functions that may be called during
      self-upgrade (`printf()` is too big for `.ramcode`), the
      `lpc178x_phy_init()` function cannot be easily used in
      `lpc178x_phy_final_reset()`. Because of this, we use a pre-set PHY
      address (`CONFIG_LPC178X_ETH_PHY_ADDR`) instead of doing automatic
      PHY discovery that is usually done in `lpc178x_phy_init()`.
      
      If Ethernet is not enabled in the U-Boot configuration file, we do not
      perform the PHY reset.
      This leads to a minor bug: if you install U-Boot without Ethernet
      support into your board and do a self-upgrade to another build of
      U-Boot with Ethernet support, the Ethernet driver will hang in the
      latter U-Boot unless you have done a full reset (by pushing the SW1
      button) after self-upgrade.
      6c05ceb4