Commit 34d45f55 authored by Alexander Potashev's avatar Alexander Potashev

RT75957. twr-k70f120m: customize the Kinetis port for TWR-K70F120M

The `board/freescale/twr-k70f120m/board.c` file was copied from
`board/freescale/twr-k60n512/board.c` without code changes, because the
Ethernet pin configuration is compatible on these two boards.

`cpu/arm_cortexm3/kinetis/clock.c` was updated to support the MCG
(Multipurpose Clock Generator) internal structure on K70 @ 120 MHz
which is different from the MCG on K60 @ 100 MHz.

The U-Boot configuration file (include/configs/twr-k70f120m.h) was
copied from the corresponding file for the TWR-K60N512 board and
customized for the TWR-K70F120M board:
    1. UART pins are different
    2. There is external RAM on the TWR-K70F120M board
    3. The in-MCU flash is 1 MB in size
    4. The clock configuration was updated (120 MHz core clock)
    5. The K70 MCU has 6 GPIO ports (instead of 5 ports on K60)
parent 4944a87c
......@@ -3217,6 +3217,9 @@ ea-lpc1788_config : unconfig
twr-k60n512_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm_cortexm3 twr-k60n512 freescale kinetis
twr-k70f120m_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm_cortexm3 twr-k70f120m freescale kinetis
#########################################################################
## XScale Systems
#########################################################################
......
#
# (C) Copyright 2011
#
# Alexander Potashev, Emcraft Systems, aspotashev@emcraft.com
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS := board.o
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
$(LIB): $(obj).depend $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
/*
* (C) Copyright 2011
*
* Alexander Potashev, Emcraft Systems, aspotashev@emcraft.com
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Board specific code for the Freescale TWR-K70F120M board
*/
#include <common.h>
#include <netdev.h>
#include <asm/arch/kinetis_gpio.h>
DECLARE_GLOBAL_DATA_PTR;
/*
* GPIO pin configuration table for TWR-K70F120M
*
* This table does not list all GPIO pins that will be configured. See also
* the code in `gpio_init()` and in the drivers (for example, the UART driver).
*/
static const struct kinetis_gpio_pin_config twr_k70f120m_gpio[] = {
#ifdef CONFIG_MCFFEC
/* A.5 = RMII0_RXER */
/*
* The pull-down resistor is not really necessary here, because this
* pin is always connected to the PHY (it is not connected by default
* on the TWR-K60N512 board.)
*/
{{KINETIS_GPIO_PORT_A, 5}, KINETIS_GPIO_CONFIG_PULLDOWN(4)},
/* A.12 = RMII0_RXD1 */
{{KINETIS_GPIO_PORT_A, 12}, KINETIS_GPIO_CONFIG_MUX(4)},
/* A.13 = RMII0_RXD0 */
{{KINETIS_GPIO_PORT_A, 13}, KINETIS_GPIO_CONFIG_MUX(4)},
/* A.14 = RMII0_CRS_DV */
{{KINETIS_GPIO_PORT_A, 14}, KINETIS_GPIO_CONFIG_MUX(4)},
/* A.15 = RMII0_TXEN */
{{KINETIS_GPIO_PORT_A, 15}, KINETIS_GPIO_CONFIG_MUX(4)},
/* A.16 = RMII0_TXD0 */
{{KINETIS_GPIO_PORT_A, 16}, KINETIS_GPIO_CONFIG_MUX(4)},
/* A.17 = RMII0_TXD1 */
{{KINETIS_GPIO_PORT_A, 17}, KINETIS_GPIO_CONFIG_MUX(4)},
/* B.0 = RMII0_MDIO */
{{KINETIS_GPIO_PORT_B, 0}, KINETIS_GPIO_CONFIG_MUX(4)},
/* B.1 = RMII0_MDC */
{{KINETIS_GPIO_PORT_B, 1}, KINETIS_GPIO_CONFIG_MUX(4)},
#endif /* CONFIG_MCFFEC */
};
/*
* Configure all necessary GPIO pins
*/
static void gpio_init(void)
{
/*
* Configure GPIO pins using the `twr_k70f120m_gpio[]` table
*/
kinetis_gpio_config_table(twr_k70f120m_gpio, ARRAY_SIZE(twr_k70f120m_gpio));
}
/*
* Early hardware init.
*/
int board_init(void)
{
/*
* Enable GPIO pins
*/
gpio_init();
return 0;
}
/*
* Dump pertinent info to the console.
*/
int checkboard(void)
{
printf("Board: Freescale TWR-K70F120M rev %s\n",
CONFIG_SYS_BOARD_REV_STR);
return 0;
}
/*
* Configure board specific parts.
*/
int misc_init_r(void)
{
/* TBD */
return 0;
}
/*
* Setup external RAM.
*/
int dram_init(void)
{
/* TBD */
return 0;
}
#ifdef CONFIG_MCFFEC
/*
* Register the Ethernet driver
*/
int board_eth_init(bd_t *bis)
{
return mcffec_initialize(bis);
}
#endif
......@@ -93,6 +93,23 @@
#undef KINETIS_MCG_PLLREFSEL /* No support for multiple oscillators */
#elif defined(CONFIG_KINETIS_K70_120MHZ)
#define KINETIS_PLL_PRDIV_MAX 8
#define KINETIS_PLL_VDIV_MIN 16
#define KINETIS_PLL_VDIV_MAX 47
#define KINETIS_PLL_REF_MIN 8 * 1000 * 1000 /* 8 MHz */
#define KINETIS_PLL_REF_MAX 16 * 1000 * 1000 /* 16 MHz */
#define KINETIS_PLL_VCO_DIV 2 /* There is a /2 divider after VCO */
#define KINETIS_CPU_RATE_MAX (120 * 1000 * 1000) /* 120 MHz */
#define KINETIS_PCLK_RATE_MAX (60 * 1000 * 1000) /* 60 MHz */
#define KINETIS_FLEXBUS_RATE_MAX (50 * 1000 * 1000) /* 50 MHz */
#define KINETIS_FLASH_RATE_MAX (25 * 1000 * 1000) /* 25 MHz */
#define KINETIS_MCG_PLLREFSEL 0 /* PLL0 input: EXTAL0 through OSC0 */
#else
#error Unsupported Freescale Kinetis MCU series
#endif
......@@ -209,6 +226,9 @@
#define KINETIS_MCG_C5_PRDIV_BITS 0
/* PLL Stop Enable */
#define KINETIS_MCG_C5_PLLSTEN_MSK (1 << 5)
/* PLL External Reference Select (for K70@120MHz) */
#define KINETIS_MCG_C5_PLLREFSEL_BIT 7
#define KINETIS_MCG_C5_PLLREFSEL_MSK (1 << KINETIS_MCG_C5_PLLREFSEL_BIT)
/*
* MCG Control 6 Register
*/
......@@ -359,10 +379,12 @@ static void clock_fei_to_fbe(void)
(KINETIS_MCG_FRDIV << KINETIS_MCG_C1_FRDIV_BITS) |
KINETIS_MCG_C1_CLKS_EXT_REF_MSK;
#ifndef CONFIG_KINETIS_OSCINIT_NOWAIT
/*
* Wait for the input from the external crystal to initialize
*/
while (!(KINETIS_MCG->status & KINETIS_MCG_S_OSCINIT_MSK));
#endif /* !CONFIG_KINETIS_OSCINIT_NOWAIT */
/*
* Wait for reference clock to switch to external reference
......@@ -390,6 +412,17 @@ static void clock_fbe_to_pbe(void)
((KINETIS_PLL_PRDIV - 1) << KINETIS_MCG_C5_PRDIV_BITS) |
KINETIS_MCG_C5_PLLSTEN_MSK;
/*
* If the Multipurpose Clock Generator (MCG) supports multiple
* oscillators (e.g. on K70 @ 120 MHz), select the necessary
* oscillator as the external reference clock for the PLL0.
*/
#ifdef KINETIS_MCG_PLLREFSEL
KINETIS_MCG->c5 =
(KINETIS_MCG->c5 & ~KINETIS_MCG_C5_PLLREFSEL_MSK) |
(KINETIS_MCG_PLLREFSEL << KINETIS_MCG_C5_PLLREFSEL_BIT);
#endif
/*
* Set the PLL multiplication factor
*/
......
......@@ -147,17 +147,40 @@ __attribute__((section(".kinetis_flash_conf"), used)) = {
/*
* Size in bytes of the flash programming acceleration RAM
*/
#if defined(CONFIG_ENVM_TYPE_K60)
#define FLASH_PROG_ACCEL_SIZE (4 * 1024)
#elif defined(CONFIG_ENVM_TYPE_K70)
#define FLASH_PROG_ACCEL_SIZE (16 * 1024)
#else
#error No CONFIG_ENVM_TYPE_XXX option defined
#endif /* CONFIG_ENVM_TYPE_XXX */
/*
* Size of the bottom half of the flash programming acceleration RAM
* that may be used for flash programming.
*/
#define FLASH_PROG_ACCEL_HALF (FLASH_PROG_ACCEL_SIZE / 2)
/*
* Size of a sector in the MCU internal flash is 2 Kbytes
* on the program flash only MCUs.
* Size of a sector in the MCU internal flash is 4 Kbytes (K70) or
* 2 Kbytes (K60) on the program flash only MCUs.
*/
#if defined(CONFIG_ENVM_TYPE_K60)
#define FLASH_SECTOR_SIZE (2 * 1024)
#elif defined(CONFIG_ENVM_TYPE_K70)
#define FLASH_SECTOR_SIZE (4 * 1024)
#else
#error No CONFIG_ENVM_TYPE_XXX option defined
#endif /* CONFIG_ENVM_TYPE_XXX */
/*
* The measurement unit for the section size used by the Program Section
* command.
*/
#if defined(CONFIG_ENVM_TYPE_K60)
#define KINETIS_ENVM_SIZE_UNIT_BITS 3 /* 8 bytes */
#elif defined(CONFIG_ENVM_TYPE_K70)
#define KINETIS_ENVM_SIZE_UNIT_BITS 4 /* 16 bytes */
#else
#error No CONFIG_ENVM_TYPE_XXX option defined
#endif /* CONFIG_ENVM_TYPE_XXX */
/*
* Offset of the byte in flash that loads into the FSEC register on reset
*/
......@@ -346,14 +369,17 @@ int __attribute__((section(".ramcode")))
kinetis_ftfl_program_section(u32 dest_addr, u32 size)
{
/*
* ">> 3": We divide `size` by 8 to convert the size in bytes into
* the size in phrases (64 bits of data).
* ">> 3" (K60): We divide `size` by 8 to convert the size in bytes
* into the size in phrases (64 bits of data).
*
* ">> 4" (K70): We divide `size` by 16 to convert the size in bytes
* into the size in double-phrases (128 bits of data).
*
* "<< 16": Then we move the two bytes inside the `data0` word,
* so that they go into the FCCOB[5:4] registers.
*/
return kinetis_ftfl_command(FTFL_CMD_PROGRAM_SECTION,
dest_addr, size << (16 - 3), 0);
dest_addr, size << (16 - KINETIS_ENVM_SIZE_UNIT_BITS), 0);
}
/*
......
......@@ -153,6 +153,11 @@
#define CONFIG_SYS_RAM_BASE 0x60000000
#define CONFIG_SYS_RAM_SIZE (32 * 1024 * 1024)
/*
* Program flash configuration
*/
#define CONFIG_ENVM_TYPE_K60
/*
* Configuration of the external Flash memory
*/
......
/*
* (C) Copyright 2011
*
* Alexander Potashev, Emcraft Systems, aspotashev@emcraft.com
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Configuration settings for the Freescale TWR-K70F120M board.
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* Disable debug messages
*/
#undef DEBUG
/*
* This is an ARM Cortex-M4 CPU core which is backward-compatible with Cortex-M3
*/
#define CONFIG_SYS_ARMCORTEXM3
/*
* This is a Kinetis-based device
*/
#define CONFIG_SYS_KINETIS
/*
* Enable GPIO driver
*/
#define CONFIG_KINETIS_GPIO
/* Number of GPIO ports (A..F on K70) */
#define KINETIS_GPIO_PORTS 6
/*
* Display CPU and Board information
*/
#define CONFIG_DISPLAY_CPUINFO 1
#define CONFIG_DISPLAY_BOARDINFO 1
#define CONFIG_SYS_BOARD_REV_STR "1"
/*
* Monitor prompt
*/
#define CONFIG_SYS_PROMPT "TWR-K70F120M> "
/*
* We want to call the CPU specific initialization
*/
#define CONFIG_ARCH_CPU_INIT
/*
* This ensures that the SoC-specific cortex_m3_soc_init() gets invoked.
*/
#define CONFIG_ARMCORTEXM3_SOC_INIT
/*
* Clock configuration (see cpu/arm_cortexm3/kinetis/clock.c for details)
*/
/* Select MCG configuration type */
#define CONFIG_KINETIS_K70_120MHZ
/* The OSCINIT0 bit does not set on K70 for a yet unknown reason */
#define CONFIG_KINETIS_OSCINIT_NOWAIT
/*
* Clock rate at the EXTAL0 input
*
* See also the description of the J19 jumper on the TWR-K70F120M board.
* The PHY clock drives EXTAL0.
*/
#define KINETIS_EXTAL_RATE 50000000
/*
* The EXTAL rate divided by the divisor value (2**10 = 1024) specified by this
* constant should be as close to the 32..40 kHz range as possible.
*/
#define KINETIS_MCG_FRDIV_POW 10
/* Core/system clock divider: 120/1 = 120 MHz */
#define KINETIS_CCLK_DIV 1
/* Peripheral clock divider: 120/2 = 60 MHz */
#define KINETIS_PCLK_DIV 2
/* FlexBus clock divider: 120/3 = 40 MHz */
#define KINETIS_FLEXBUS_CLK_DIV 3
/* Flash clock divider: 120/5 = 24 MHz */
#define KINETIS_FLASH_CLK_DIV 5
/* PLL input divider: 50/5 = 10 MHz */
#define KINETIS_PLL_PRDIV 5
/* PLL multiplier: 10*24/2 = 120 MHz */
#define KINETIS_PLL_VDIV 24
/*
* Number of clock ticks in 1 sec
*/
#define CONFIG_SYS_HZ 1000
/*
* The SYSTICK Timer's clock source is always the core clock, the MCU hardware
* does not allow to change this.
*/
#define CONFIG_ARMCORTEXM3_SYSTICK_CPU
/*
* Enable/disable h/w watchdog
*/
#undef CONFIG_HW_WATCHDOG
/*
* No interrupts
*/
#undef CONFIG_USE_IRQ
/*
* Memory layout configuration
*/
#define CONFIG_MEM_NVM_BASE 0x00000000
#define CONFIG_MEM_NVM_LEN (1024 * 1024)
/*
* 128 kB of SRAM centered at 0x20000000
* SRAM_L: 0x1FFF0000 - 0x1FFFFFFF (64 kB)
* SRAM_U: 0x20000000 - 0x2000FFFF (64 kB)
*/
#define CONFIG_MEM_RAM_BASE 0x1FFF0000
#define CONFIG_MEM_RAM_LEN (22 * 1024)
#define CONFIG_MEM_RAM_BUF_LEN (84 * 1024)
#define CONFIG_MEM_MALLOC_LEN (18 * 1024)
#define CONFIG_MEM_STACK_LEN (4 * 1024)
/*
* malloc() pool size
*/
#define CONFIG_SYS_MALLOC_LEN CONFIG_MEM_MALLOC_LEN
/*
* Configuration of the external DDR2 SDRAM memory
*/
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_RAM_CS 0
#define CONFIG_SYS_RAM_BASE 0x80000000
#define CONFIG_SYS_RAM_SIZE (128 * 1024 * 1024)
/*
* Program flash configuration
*/
#define CONFIG_ENVM_TYPE_K70
/*
* Configuration of the external Flash memory
*/
#define CONFIG_SYS_NO_FLASH
/*
* Store env in memory only
*/
#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_SIZE (4 * 1024)
#define CONFIG_ENV_ADDR CONFIG_SYS_FLASH_BANK1_BASE
#define CONFIG_INFERNO 1
#define CONFIG_ENV_OVERWRITE 1
/*
* Serial console configuration
*/
#define CONFIG_KINETIS_UART_CONSOLE
/*
* UART2 is connected to the RS-232 port on the TWR-SER board
* UART2 pin configuration: Rx: PORT_E.17, Tx = PORT_E.16
*/
#define CONFIG_KINETIS_UART_PORT 2 /* UART2 */
#define CONFIG_KINETIS_UART_RX_IO_PORT 4 /* PORT E */
#define CONFIG_KINETIS_UART_RX_IO_PIN 17 /* pin 17 */
#define CONFIG_KINETIS_UART_RX_IO_FUNC 3 /* UART2_RX */
#define CONFIG_KINETIS_UART_TX_IO_PORT 4 /* PORT E */
#define CONFIG_KINETIS_UART_TX_IO_PIN 16 /* pin 16 */
#define CONFIG_KINETIS_UART_TX_IO_FUNC 3 /* UART2_TX */
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/*
* Ethernet configuration
*/
#define CONFIG_MCFFEC
/* Only the RMII mode is possible on the TWR-K70F120M board */
#undef CONFIG_MCFFEC_MII
#define CONFIG_NET_MULTI
#define CONFIG_MII
#define CONFIG_MII_INIT
/*
* The value of CONFIG_SYS_FEC0_PINMUX does not matter.
* This configuration option is required by the `mcffec.c` driver.
*/
#define CONFIG_SYS_FEC0_PINMUX 0
#define CONFIG_SYS_FEC0_IOBASE 0x400C0000
#define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
/*
* Ethernet buffer descriptor tables should be aligned on 512-byte boundaries
*/
#define CONFIG_SYS_CACHELINE_SIZE 512
#define MCFFEC_TOUT_LOOP 1000000
#define CONFIG_SYS_DISCOVER_PHY
#define CONFIG_SYS_RX_ETH_BUFFER 8
/*
* Options for the MDC clock
*/
/* Internal MAC clock rate */
#define CONFIG_MCFFEC_MAC_CLK clock_get(CLOCK_MACCLK)
/*
* We limit the MDC rate to 800 kHz, because the rate of 2.5 MHz leads to data
* corruption when reading the PHY registers (we experienced data corruptions
* on TWR-K60N512.)
*/
#define CONFIG_MCFFEC_MII_SPEED_LIMIT 800000
/*
* Console I/O buffer size
*/
#define CONFIG_SYS_CBSIZE 256
/*
* Print buffer size
*/
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_RAM_BASE
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_RAM_BASE + \
CONFIG_SYS_RAM_SIZE)
/*
* Needed by "loadb"
*/
#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_RAM_BASE
/*
* Monitor is actually in eNVM. In terms of U-Boot, it is neither "flash",
* not RAM, but CONFIG_SYS_MONITOR_BASE must be defined.
*/
#define CONFIG_SYS_MONITOR_BASE 0x0
/*
* Monitor is not in flash. Needs to define this to prevent
* U-Boot from running flash_protect() on the monitor code.
*/
#define CONFIG_MONITOR_IS_IN_RAM 1
/*
* Enable all those monitor commands that are needed
*/
#include <config_cmd_default.h>
#undef CONFIG_CMD_BOOTD
#undef CONFIG_CMD_CONSOLE
#undef CONFIG_CMD_ECHO
#undef CONFIG_CMD_EDITENV
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_IMI
#undef CONFIG_CMD_ITEST
#undef CONFIG_CMD_IMLS
#undef CONFIG_CMD_LOADS
#undef CONFIG_CMD_MISC
#define CONFIG_CMD_NET
#undef CONFIG_CMD_NFS
#undef CONFIG_CMD_SOURCE
#undef CONFIG_CMD_XIMG
/*
* To save memory disable long help
*/
#undef CONFIG_SYS_LONGHELP
/*
* Max number of command args
*/
#define CONFIG_SYS_MAXARGS 16
/*
* Auto-boot sequence configuration
*/
#define CONFIG_BOOTDELAY 3
#define CONFIG_ZERO_BOOTDELAY_CHECK
#define CONFIG_HOSTNAME twr-k70f120m
#define CONFIG_BOOTARGS "kinetis_platform=twr-k70f120m "\
"console=ttyS0,115200 panic=10 mem=16M"
#define CONFIG_BOOTCOMMAND "run flashboot"
/*
* This ensures that the board-specific misc_init_r() gets invoked.
*/
#define CONFIG_MISC_INIT_R
/*
* Short-cuts to some useful commands (macros)
*/
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=0x80000000\0" \
"addip=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:" \
"${netmask}:${hostname}:eth0:off\0" \
"ethaddr=C0:B1:3C:77:88:AA\0" \
"ipaddr=172.17.6.36\0" \
"serverip=172.17.0.1\0" \
"image=k70/uImage\0" \
"netboot=tftp ${image};run addip;bootm\0" \
"update=tftp ${image};" \
"prot off ${flashaddr} +${filesize};" \
"era ${flashaddr} +${filesize};" \
"cp.b ${loadaddr} ${flashaddr} ${filesize}\0"
/*
* Linux kernel boot parameters configuration
*/
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_CMDLINE_TAG
#endif /* __CONFIG_H */
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