Commit 3b364a78 authored by Yuri Tikhonov's avatar Yuri Tikhonov

RM-1130 STM32F746-Discovery: enable QSPI Flash

Signed-off-by: default avatarYuri Tikhonov <yur@emcraft.com>
parent 189d4c3b
......@@ -39,6 +39,7 @@
#include <asm/system.h>
#include <asm/arch/fsmc.h>
#include <linux/mtd/stm32_qspi.h>
DECLARE_GLOBAL_DATA_PTR;
......@@ -202,6 +203,19 @@ static const struct stm32f2_gpio_dsc ltdc_iomux[] = {
};
#endif /* CONFIG_VIDEO_STM32F4_LTDC */
#ifdef CONFIG_STM32_QSPI
static const struct stm32f2_gpio_dsc qspi_af9_iomux[] = {
{STM32F2_GPIO_PORT_D, STM32F2_GPIO_PIN_11}, /* D0 */
{STM32F2_GPIO_PORT_D, STM32F2_GPIO_PIN_12}, /* D1 */
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_2}, /* D2 */
{STM32F2_GPIO_PORT_D, STM32F2_GPIO_PIN_13}, /* D3 */
{STM32F2_GPIO_PORT_B, STM32F2_GPIO_PIN_2}, /* CLK */
};
static const struct stm32f2_gpio_dsc qspi_af10_iomux[] = {
{STM32F2_GPIO_PORT_B, STM32F2_GPIO_PIN_6}, /* NCS */
};
#endif /* CONFIG_STM32_QSPI */
/*
* Init FMC/FSMC GPIOs based
*/
......@@ -248,6 +262,29 @@ static int ltdc_setup_iomux(void)
}
#endif /* CONFIG_VIDEO_STM32F4_LTDC */
#ifdef CONFIG_STM32_QSPI
static int qspi_setup_iomux(void)
{
int i, rv = 0;
for (i = 0; i < ARRAY_SIZE(qspi_af9_iomux); i++) {
rv = stm32f2_gpio_config(&qspi_af9_iomux[i],
STM32F2_GPIO_ROLE_QSPI_AF9);
if (rv)
break;
}
for (i = 0; i < ARRAY_SIZE(qspi_af10_iomux); i++) {
rv = stm32f2_gpio_config(&qspi_af10_iomux[i],
STM32F2_GPIO_ROLE_QSPI_AF10);
if (rv)
break;
}
return rv;
}
#endif /* CONFIG_STM32_QSPI */
/*
* Early hardware init.
*/
......@@ -276,6 +313,12 @@ int board_init(void)
return rv;
#endif /* CONFIG_VIDEO_STM32F4_LTDC */
#ifdef CONFIG_STM32_QSPI
rv = qspi_setup_iomux();
if (rv)
return rv;
#endif
return 0;
}
......@@ -437,3 +480,18 @@ int board_eth_init(bd_t *bis)
}
#endif
#ifdef BOARD_LATE_INIT
int board_late_init(void)
{
int rv = 0;
#ifdef CONFIG_STM32_QSPI
STM32_RCC->ahb3enr |= RCC_AHB3ENR_QSPIEN;
STM32_RCC->ahb1enr |= RCC_AHB1ENR_DMA1EN | RCC_AHB1ENR_DMA2EN;
rv = stm32_qspi_init();
#endif
return rv;
}
#endif /* BOARD_LATE_INIT */
......@@ -105,8 +105,6 @@ struct stm32_qspi_regs {
#define QSPI_TIMEOUT_MS 1000
#define QSPI_POLLING_INTERVAL 16
#define QSPI_FAST_READ_DUMMY_CYCLES 6
struct stm32_qspi_priv {
struct stm32_qspi_regs *regs;
size_t size;
......@@ -367,7 +365,7 @@ static int write_page(struct stm32_qspi_priv *priv, u32 address, const u8 *buf,
writel(size - 1, &priv->regs->dlr);
writel(QSPI_CCR_FMODE_INDIRECT_WRITE
| SPINOR_OP_FAST_PROGRAM
| CONFIG_STM32_QSPI_FAST_PROGRAM_CMD
| QSPI_CCR_IMODE_SINGLE_LINE
| QSPI_CCR_ADMODE_FOUR_LINES
| QSPI_CCR_ADSIZE_THREE_BYTES
......@@ -490,7 +488,7 @@ int stm32_qspi_init(void)
stm32_qspi->regs = (struct stm32_qspi_regs *)(uintptr_t)STM32_QSPI_BASE;
stm32_qspi->fast_read_dummy = QSPI_FAST_READ_DUMMY_CYCLES;
stm32_qspi->fast_read_dummy = CONFIG_STM32_QSPI_FAST_READ_DUMMY_CYCLES;
stm32_qspi->size = 1 << CONFIG_SPI_FLASH_SIZE_OFF;
stm32_qspi->erase_size = SPINOR_MAX_ERASE_SIZE;
stm32_qspi->write_size = SPINOR_MAX_WRITE_SIZE;
......@@ -561,7 +559,8 @@ int do_qspi(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
}
printf("Erase QSPI flash from 0x%lx to 0x%lx, estimated time %lu s\n",
off, off + size,
(MT25Q_64KB_ERASE_TYP_TIME_MS * size) / stm32_qspi->erase_size / 1000);
(CONFIG_STM32_QSPI_64KB_ERASE_TYP_TIME_MS * size) /
stm32_qspi->erase_size / 1000);
err = erase(stm32_qspi, off, size);
printf("Erase QSPI flash: %s\n", err ? "FAIL" : "OK");
} else {
......@@ -578,7 +577,8 @@ int do_qspi(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
&& str2long(argv[4], &size)) {
printf("Write from memory 0x%lx to QSPI 0x%lx, size 0x%lx, estimated time %lu s\n",
addr, off, size,
(MT25Q_256B_PROGRAM_TYP_TIME_US * size) / stm32_qspi->write_size / 1000 / 1000);
(CONFIG_STM32_QSPI_256B_PROGRAM_TYP_TIME_US * size) /
stm32_qspi->write_size / 1000 / 1000);
err = write(stm32_qspi, off, (u8*)addr, size);
printf("Write from memory to QSPI: %s\n", err ? "FAIL" : "OK");
} else {
......
/*
* (C) Copyright 2011-2015
* (C) Copyright 2011-2017
*
* Yuri Tikhonov, Emcraft Systems, yur@emcraft.com
* Alexander Potashev, Emcraft Systems, aspotashev@emcraft.com
......@@ -30,6 +30,11 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#include <linux/mtd/stm32_qspi.h>
#define stringify(s) tostring(s)
#define tostring(s) #s
/*
* Disable debug messages
*/
......@@ -68,11 +73,19 @@
*/
#define CONFIG_SYS_PROMPT "STM32F746-DISCO> "
/*
* For "&&" support in commands in env variables
*/
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
/*
* We want to call the CPU specific initialization
*/
#define CONFIG_ARCH_CPU_INIT
#define BOARD_LATE_INIT
/*
* Clock configuration (see mach-stm32/clock.c for details):
* - use PLL as the system clock;
......@@ -87,6 +100,20 @@
#define CONFIG_STM32_PLL_P 2
#define CONFIG_STM32_PLL_Q 8
#define CONFIG_SPI
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_SIZE_OFF 24 /* 2^24 = 16MiB */
#define CONFIG_STM32_QSPI
#define CONFIG_STM32_QSPI_FREQ 100000000 /* max we can get from HCLK=200MHz */
/*
* N25Q Flash specific configs
*/
#define CONFIG_STM32_QSPI_FAST_READ_DUMMY_CYCLES 10
#define CONFIG_STM32_QSPI_FAST_PROGRAM_CMD 0x12
#define CONFIG_STM32_QSPI_64KB_ERASE_TYP_TIME_MS 700
#define CONFIG_STM32_QSPI_256B_PROGRAM_TYP_TIME_US 500
/*
* Number of clock ticks in 1 sec
*/
......@@ -232,10 +259,12 @@
/*
* Store env in Flash memory
* CONFIG_ENV_SIZE = 4 * 1024
* CONFIG_ENV_ADDR = CONFIG_SYS_ENVM_BASE + (128 * 1024)
*/
#define CONFIG_ENV_IS_IN_ENVM
#define CONFIG_ENV_SIZE (4 * 1024)
#define CONFIG_ENV_ADDR (CONFIG_SYS_ENVM_BASE + (128 * 1024))
#define CONFIG_ENV_SIZE 0x1000
#define CONFIG_ENV_ADDR 0x8020000
#define CONFIG_INFERNO 1
#define CONFIG_ENV_OVERWRITE 1
......@@ -352,7 +381,7 @@
#include <config_cmd_default.h>
#undef CONFIG_CMD_BOOTD
#undef CONFIG_CMD_CONSOLE
#undef CONFIG_CMD_ECHO
#define CONFIG_CMD_ECHO
#undef CONFIG_CMD_EDITENV
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_IMI
......@@ -380,19 +409,29 @@
*/
#define CONFIG_BOOTDELAY 3
#define CONFIG_ZERO_BOOTDELAY_CHECK
#define CONFIG_BOOTCOMMAND "run netboot"
#define CONFIG_BOOTCOMMAND "run qspiboot || echo 'Boot from QSPI failed, run the update_kernel command'"
/* boot args and env */
#define CONFIG_HOSTNAME stm32f7-disco
#define CONFIG_BOOTARGS "stm32_platform=stm32f7-disco " \
"console=ttyS5,115200 panic=10"
#define CONFIG_BOOTARGS "stm32_platform=stm32f7-disco console=ttyS5,115200 panic=10"
#define LOADADDR "0xC0007FC0"
#define REV_EXTRA_ENV \
"envmboot=run args addip;bootm ${envmaddr}\0" \
"envmupdate=tftp ${image};" \
"cptf ${envmaddr} ${loadaddr} ${filesize}\0"
#define REV_EXTRA_ENV \
"netboot=tftp ${image} && run args addip && bootm\0" \
"qspiboot=echo 'Booting from QSPI'" \
" && cp.b " stringify(STM32_QSPI_BANK) " ${loadaddr} ${kernel_size}" \
" && run args addip && bootm\0" \
"update_uboot=tftp ${uboot_image}" \
" && cptf " stringify(CONFIG_MEM_NVM_BASE) " ${loadaddr} ${filesize} do_reset\0" \
"update_kernel=tftp ${image}" \
" && qspi erase 0 ${filesize}" \
" && qspi write ${loadaddr} 0 ${filesize}" \
" && setenv kernel_size ${filesize}" \
" && saveenv" \
" && echo 'Successfully updated'\0" \
"env_default=mw.b ${loadaddr} 0xFF " stringify(CONFIG_ENV_SIZE) "" \
" && cptf ${envmaddr} ${loadaddr} " stringify(CONFIG_ENV_SIZE) "\0"
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
......@@ -403,13 +442,13 @@
"loadaddr=" LOADADDR "\0" \
"args=setenv bootargs " CONFIG_BOOTARGS "\0" \
"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:eth0:off\0" \
"envmaddr=08040000\0" \
"envmaddr=" stringify(CONFIG_ENV_ADDR) "\0" \
"ethaddr=C0:B1:3C:88:88:85\0" \
"ipaddr=172.17.4.206\0" \
"serverip=172.17.0.1\0" \
"image=stm32f7/uImage\0" \
"uboot_image=stm32f7/f746-disco.u-boot.bin\0" \
"stdin=serial\0" \
"netboot=tftp ${image};run args addip;bootm\0" \
REV_EXTRA_ENV
/*
......
......@@ -103,8 +103,13 @@
#define CONFIG_STM32_QSPI
#define CONFIG_STM32_QSPI_FREQ 108000000
#define MT25Q_64KB_ERASE_TYP_TIME_MS 150
#define MT25Q_256B_PROGRAM_TYP_TIME_US 350
/*
* MT25Q Flash specific configs
*/
#define CONFIG_STM32_QSPI_FAST_READ_DUMMY_CYCLES 6
#define CONFIG_STM32_QSPI_FAST_PROGRAM_CMD 0x38
#define CONFIG_STM32_QSPI_64KB_ERASE_TYP_TIME_MS 150
#define CONFIG_STM32_QSPI_256B_PROGRAM_TYP_TIME_US 350
/*
* Number of clock ticks in 1 sec
......
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