Commit 55246688 authored by Alexander Potashev's avatar Alexander Potashev

RT77744. lpc4350-eval: Basic port

Support the following features:
 * Serial console on USART0.
 * Common pin configuration functions (needed for USART0).
 * Clock configuration: The Cortex-M4 core runs at 204 MHz.
 * `cptf` command is technically available, but has no effect since there is no
internal flash on LPC18x0/LPC43x0 MCUs.
 * The lowest SRAM region (128 KB at 0x10000000) is reserved for the currently
running U-Boot image.
parent baf57570
......@@ -3232,6 +3232,9 @@ lpc-lnx-evb_config : unconfig
k70-som_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm_cortexm3 k70-som emcraft kinetis
lpc4350-eval_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm_cortexm3 lpc4350-eval hitex lpc18xx
#########################################################################
## XScale Systems
#########################################################################
......
#
# (C) Copyright 2011
#
# Alexander Potashev, Emcraft Systems, aspotashev@emcraft.com
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS := board.o
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
$(LIB): $(obj).depend $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
/*
* (C) Copyright 2012
*
* Alexander Potashev, Emcraft Systems, aspotashev@emcraft.com
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Board specific code for the Hitex LPC4350 Eval board
*/
#include <common.h>
#include <netdev.h>
#include <asm/arch/lpc18xx_gpio.h>
/*
* Pin configuration table for Hitex LPC4350 Eval.
*
* This table does not list all MCU pins that will be configured. See also
* the code in `iomux_init()`.
*/
static const struct lpc18xx_pin_config hitex_lpc4350_iomux[] = {
/*
* Pin configuration for UART
*/
{{CONFIG_LPC18XX_UART_TX_IO_GROUP, CONFIG_LPC18XX_UART_TX_IO_PIN},
LPC18XX_IOMUX_CONFIG(1, 0, 1, 0, 0, 0)},
{{CONFIG_LPC18XX_UART_RX_IO_GROUP, CONFIG_LPC18XX_UART_RX_IO_PIN},
LPC18XX_IOMUX_CONFIG(1, 0, 1, 0, 1, 0)},
};
/*
* Configure all necessary MCU pins
*/
static void iomux_init(void)
{
/*
* Configure GPIO pins using the `hitex_lpc4350_iomux[]` table
*/
lpc18xx_pin_config_table(
hitex_lpc4350_iomux, ARRAY_SIZE(hitex_lpc4350_iomux));
}
/*
* Early hardware init.
*/
int board_init(void)
{
/*
* Configure MCU pins
*/
iomux_init();
return 0;
}
/*
* Dump pertinent info to the console.
*/
int checkboard(void)
{
printf("Board: Hitex LPC4350 Eval rev %s\n",
CONFIG_SYS_BOARD_REV_STR);
return 0;
}
/*
* Configure board specific parts.
*/
#ifdef CONFIG_MISC_INIT_R
int misc_init_r(void)
{
/* TBD */
return 0;
}
#endif /* CONFIG_MISC_INIT_R */
/*
* Setup external RAM.
*/
int dram_init(void)
{
return 0;
}
......@@ -60,6 +60,8 @@ int arch_cpu_init(void)
gd->bd->bi_arch_number = MACH_TYPE_STM32;
#elif defined(CONFIG_SYS_LPC178X)
gd->bd->bi_arch_number = MACH_TYPE_LPC178X;
#elif defined(CONFIG_SYS_LPC18XX)
gd->bd->bi_arch_number = MACH_TYPE_LPC18XX;
#elif defined(CONFIG_SYS_KINETIS)
gd->bd->bi_arch_number = MACH_TYPE_KINETIS;
#else
......
#
# (C) Copyright 2000-2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2012
# Port to NXP LPC18xx MCU
# Alexander Potashev, Emcraft Systems, aspotashev@emcraft.com.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).a
COBJS := clock.o cpu.o envm.o wdt.o
SOBJS :=
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean:
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################
/*
* (C) Copyright 2012
*
* Alexander Potashev, Emcraft Systems, aspotashev@emcraft.com
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include "clock.h"
/*
* PLL0* register map
* Used for PLL0USB at 0x4005001C and for PLL0AUDIO at 0x4005002C.
*
* This structure is 0x10 bytes long, it is important when it embedding into
* `struct lpc18xx_cgu_regs`.
*/
struct lpc18xx_pll0_regs {
u32 stat; /* PLL status register */
u32 ctrl; /* PLL control register */
u32 mdiv; /* PLL M-divider register */
u32 np_div; /* PLL N/P-divider register */
};
/*
* CGU (Clock Generation Unit) register map
* Should be mapped at 0x40050000.
*/
struct lpc18xx_cgu_regs {
u32 rsv0[5];
u32 freq_mon; /* Frequency monitor */
u32 xtal_osc_ctrl; /* XTAL oscillator control */
struct lpc18xx_pll0_regs pll0usb; /* PLL0USB registers */
struct lpc18xx_pll0_regs pll0audio; /* PLL0AUDIO registers */
u32 pll0audio_frac; /* PLL0AUDIO fractional divider */
u32 pll1_stat; /* PLL1 status register */
u32 pll1_ctrl; /* PLL1 control register */
u32 idiv[5]; /* IDIVA_CTRL .. IDIVE_CTRL */
/* BASE_* clock configuration registers */
u32 safe_clk;
u32 usb0_clk;
u32 periph_clk;
u32 usb1_clk;
u32 m4_clk;
u32 spifi_clk;
u32 spi_clk;
u32 phy_rx_clk;
u32 phy_tx_clk;
u32 apb1_clk;
u32 apb3_clk;
u32 lcd_clk;
u32 vadc_clk;
u32 sdio_clk;
u32 ssp0_clk;
u32 ssp1_clk;
u32 uart0_clk;
u32 uart1_clk;
u32 uart2_clk;
u32 uart3_clk;
u32 out_clk;
u32 rsv1[4];
u32 apll_clk;
u32 cgu_out0_clk;
u32 cgu_out1_clk;
};
/*
* CGU registers base
*/
#define LPC18XX_CGU_BASE 0x40050000
#define LPC18XX_CGU ((volatile struct lpc18xx_cgu_regs *) \
LPC18XX_CGU_BASE)
/*
* Bit offsets in Clock Generation Unit (CGU) registers
*/
/*
* Crystal oscillator control register (XTAL_OSC_CTRL)
*/
/* Oscillator-pad enable */
#define LPC18XX_CGU_XTAL_ENABLE (1 << 0)
/* Select frequency range */
#define LPC18XX_CGU_XTAL_HF (1 << 2)
#if (CONFIG_LPC18XX_EXTOSC_RATE < 10000000) || \
(CONFIG_LPC18XX_EXTOSC_RATE > 25000000)
#error CONFIG_LPC18XX_EXTOSC_RATE is out of range for PLL1
#endif
/*
* For all CGU clock registers
*/
/* CLK_SEL: Clock source selection */
#define LPC18XX_CGU_CLKSEL_BITS 24
#define LPC18XX_CGU_CLKSEL_MSK (0x1f << LPC18XX_CGU_CLKSEL_BITS)
/* Crystal oscillator */
#define LPC18XX_CGU_CLKSEL_XTAL (0x06 << LPC18XX_CGU_CLKSEL_BITS)
/* PLL1 */
#define LPC18XX_CGU_CLKSEL_PLL1 (0x09 << LPC18XX_CGU_CLKSEL_BITS)
/* Block clock automatically during frequency change */
#define LPC18XX_CGU_AUTOBLOCK_MSK (1 << 11)
/*
* PLL1 control register
*/
/* Power-down */
#define LPC18XX_CGU_PLL1CTRL_PD_MSK (1 << 0)
/* Input clock bypass control */
#define LPC18XX_CGU_PLL1CTRL_BYPASS_MSK (1 << 1)
/* PLL feedback select */
#define LPC18XX_CGU_PLL1CTRL_FBSEL_MSK (1 << 6)
/* PLL direct CCO output */
#define LPC18XX_CGU_PLL1CTRL_DIRECT_MSK (1 << 7)
/* Post-divider division ratio P. The value applied is 2**P. */
#define LPC18XX_CGU_PLL1CTRL_PSEL_BITS 8
#define LPC18XX_CGU_PLL1CTRL_PSEL_MSK \
(3 << LPC18XX_CGU_PLL1CTRL_PSEL_BITS)
/* Pre-divider division ratio */
#define LPC18XX_CGU_PLL1CTRL_NSEL_BITS 12
#define LPC18XX_CGU_PLL1CTRL_NSEL_MSK \
(3 << LPC18XX_CGU_PLL1CTRL_NSEL_BITS)
/* Feedback-divider division ratio (M) */
#define LPC18XX_CGU_PLL1CTRL_MSEL_BITS 16
#define LPC18XX_CGU_PLL1CTRL_MSEL_MSK \
(0xff << LPC18XX_CGU_PLL1CTRL_MSEL_BITS)
/*
* PLL1 status register
*/
/* PLL1 lock indicator */
#define LPC18XX_CGU_PLL1STAT_LOCK (1 << 0)
/*
* Clock values
*/
static u32 clock_val[CLOCK_END];
/*
* Set LPC18XX_PLL1_CLK_OUT to the output rate of PLL1
*/
#define LPC18XX_PLL1_CLK_OUT \
(CONFIG_LPC18XX_EXTOSC_RATE * CONFIG_LPC18XX_PLL1_M)
/*
* Compile time sanity checks for defined board clock setup
*/
#ifndef CONFIG_LPC18XX_EXTOSC_RATE
#error CONFIG_LPC18XX_EXTOSC_RATE is not set, set to the external osc rate
#endif
/*
* Verify that the request PLL1 output frequency fits the range
* of 156 MHz to 320 MHz, so that the PLL1 Direct Mode is applicable.
* Our clock configuration code (`clock_setup()`) support only this mode.
*/
#if LPC18XX_PLL1_CLK_OUT < 156000000
#error Requested PLL1 output frequency is too low
#endif
#if LPC18XX_PLL1_CLK_OUT > 320000000
#error Requested PLL1 output frequency is too high
#endif
/*
* We cannot change the PLL1 multiplier value immediately to the maximum, it has
* to be increased in two steps. The following is the value for the first step.
*/
#define LPC18XX_PLL1_M_INTERMEDIATE 9
/*
* Use this function to implement delays until the clock system is initialized
*/
static void cycle_delay(int n)
{
volatile int i;
for (i = 0; i < n; i++);
}
/*
* Set-up the external crystal oscillator, PLL1, CPU core clock and
* all necessary clocks for peripherals.
*/
static void clock_setup(void)
{
/*
* Configure and enable the external crystal oscillator
*/
#if CONFIG_LPC18XX_EXTOSC_RATE > 15000000
LPC18XX_CGU->xtal_osc_ctrl |= LPC18XX_CGU_XTAL_HF;
#else
LPC18XX_CGU->xtal_osc_ctrl &= ~LPC18XX_CGU_XTAL_HF;
#endif
LPC18XX_CGU->xtal_osc_ctrl &= ~LPC18XX_CGU_XTAL_ENABLE;
/*
* Wait for the external oscillator to stabilize
*/
cycle_delay(5000);
/*
* Switch the M4 core clock to the 12MHz external oscillator
*/
LPC18XX_CGU->m4_clk =
(LPC18XX_CGU->m4_clk & ~LPC18XX_CGU_CLKSEL_MSK) |
LPC18XX_CGU_CLKSEL_XTAL | LPC18XX_CGU_AUTOBLOCK_MSK;
/*
* Reset PLL1 configuration
*/
LPC18XX_CGU->pll1_ctrl =
(LPC18XX_CGU->pll1_ctrl &
~LPC18XX_CGU_CLKSEL_MSK &
~LPC18XX_CGU_PLL1CTRL_PSEL_MSK &
~LPC18XX_CGU_PLL1CTRL_NSEL_MSK &
~LPC18XX_CGU_PLL1CTRL_MSEL_MSK &
~LPC18XX_CGU_PLL1CTRL_BYPASS_MSK) |
LPC18XX_CGU_CLKSEL_XTAL;
/*
* Intermediate PLL1 configuration, do not reach the desired output rate
* at this point.
*/
LPC18XX_CGU->pll1_ctrl |=
LPC18XX_CGU_PLL1CTRL_FBSEL_MSK |
LPC18XX_CGU_PLL1CTRL_DIRECT_MSK |
(0 << LPC18XX_CGU_PLL1CTRL_NSEL_BITS) |
((LPC18XX_PLL1_M_INTERMEDIATE - 1) <<
LPC18XX_CGU_PLL1CTRL_MSEL_BITS);
/*
* Enable PLL1 if it was disabled
*/
LPC18XX_CGU->pll1_ctrl &= ~LPC18XX_CGU_PLL1CTRL_PD_MSK;
/*
* Wait for the PLL1 lock detector
*/
while (!(LPC18XX_CGU->pll1_stat & LPC18XX_CGU_PLL1STAT_LOCK));
/*
* Use PLL1 as clock source for BASE_M4_CL and BASE_UARTx_CLK
*/
LPC18XX_CGU->m4_clk = LPC18XX_CGU_CLKSEL_PLL1 |
LPC18XX_CGU_AUTOBLOCK_MSK;
LPC18XX_CGU->uart0_clk = LPC18XX_CGU_CLKSEL_PLL1 |
LPC18XX_CGU_AUTOBLOCK_MSK;
LPC18XX_CGU->uart1_clk = LPC18XX_CGU_CLKSEL_PLL1 |
LPC18XX_CGU_AUTOBLOCK_MSK;
LPC18XX_CGU->uart2_clk = LPC18XX_CGU_CLKSEL_PLL1 |
LPC18XX_CGU_AUTOBLOCK_MSK;
LPC18XX_CGU->uart3_clk = LPC18XX_CGU_CLKSEL_PLL1 |
LPC18XX_CGU_AUTOBLOCK_MSK;
/*
* Raise PLL1 multiplier to the requested value
*/
LPC18XX_CGU->pll1_ctrl =
(LPC18XX_CGU->pll1_ctrl & ~LPC18XX_CGU_PLL1CTRL_MSEL_MSK) |
((CONFIG_LPC18XX_PLL1_M - 1) <<
LPC18XX_CGU_PLL1CTRL_MSEL_BITS);
}
/*
* Initialize the reference clocks.
*/
void clock_init(void)
{
clock_setup();
/*
* Set SysTick timer rate to the CPU core clock
*/
clock_val[CLOCK_SYSTICK] = LPC18XX_PLL1_CLK_OUT;
/*
* Set the CPU core clock
*/
clock_val[CLOCK_CCLK] = LPC18XX_PLL1_CLK_OUT;
/*
* Set UARTx base clock rate
*/
clock_val[CLOCK_UART0] = LPC18XX_PLL1_CLK_OUT;
clock_val[CLOCK_UART1] = LPC18XX_PLL1_CLK_OUT;
clock_val[CLOCK_UART2] = LPC18XX_PLL1_CLK_OUT;
clock_val[CLOCK_UART3] = LPC18XX_PLL1_CLK_OUT;
}
/*
* Return a clock value for the specified clock.
*
* @param clck id of the clock
* @returns frequency of the clock
*/
unsigned long clock_get(enum clock clck)
{
return clock_val[clck];
}
/*
* (C) Copyright 2012
*
* Alexander Potashev, Emcraft Systems, aspotashev@emcraft.com
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/arch/lpc18xx.h>
#include "clock.h"
/*
* Print the CPU specific information
*/
int print_cpuinfo(void)
{
char buf[2][32];
#if defined(CONFIG_SYS_ARMCORTEXM4)
printf("CPU : %s\n", "LPC43xx series (Cortex-M4/M0)");
#else
printf("CPU : %s\n", "LPC18xx series (Cortex-M3)");
#endif
strmhz(buf[0], clock_get(CLOCK_SYSTICK));
strmhz(buf[1], clock_get(CLOCK_CCLK));
printf("Freqs: SYSTICK=%sMHz,CCLK=%sMHz\n",
buf[0], buf[1]);
return 0;
}
/*
* (C) Copyright 2012
*
* Alexander Potashev, Emcraft Systems, aspotashev@emcraft.com
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <errno.h>
#include "envm.h"
/*
* Initialize internal Flash interface
*
* This function should not be in .ramcode, because it will be called only once
* before self-upgrade.
*/
void envm_init(void)
{
}
/*
* Write a data buffer to internal Flash.
* Note that we need for this function to reside in RAM since it
* will be used to self-upgrade U-boot in internal Flash.
*/
u32
#ifdef CONFIG_ARMCORTEXM3_RAMCODE
__attribute__((section(".ramcode")))
__attribute__((long_call))
#endif
envm_write(u32 offset, void *buf, u32 size)
{
printf("Error: Internal flash is not supported "
"on LPC18xx and LPC43xx.\n");
return -ENODEV;
}
/*
* (C) Copyright 2011
*
* Alexander Potashev, Emcraft Systems, aspotashev@emcraft.com
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include "wdt.h"
/*
* Strobe the WDT.
*/
void wdt_strobe(void)
{
/*
* TBD
*/
return;
}
/*
* Disable the WDT.
*/
void wdt_disable(void)
{
/*
* TBD
*/
return;
}
/*
* Enable the WDT.
*/
void wdt_enable(void)
{
/*
* TBD
*/
return;
}
......@@ -31,6 +31,7 @@ COBJS-$(CONFIG_MX31_GPIO) += mx31_gpio.o
COBJS-$(CONFIG_PCA953X) += pca953x.o
COBJS-$(CONFIG_STM32F2_GPIO) += stm32f2_gpio.o
COBJS-$(CONFIG_LPC178X_GPIO) += lpc178x_gpio.o
COBJS-$(CONFIG_LPC18XX_GPIO) += lpc18xx_gpio.o
COBJS-$(CONFIG_KINETIS_GPIO) += kinetis_gpio.o
COBJS := $(COBJS-y)
......
/*
* (C) Copyright 2012
*
* Alexander Potashev, Emcraft Systems, aspotashev@emcraft.com
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/errno.h>
#include <asm/arch/lpc18xx_gpio.h>
DECLARE_GLOBAL_DATA_PTR;
/*
* 16 pin groups. Number of pins in each group is limited to 32.
*/
/* Number of IOMUX pin groups */
#define LPC18XX_IOMUX_GROUPS 16
/* Maximum number of pins in each group */
#define LPC18XX_IOMUX_GROUP_PINS 32
/*
* System Control Unit (SCU) registers base
*/
#define LPC18XX_SCU_BASE (LPC18XX_APB0PERIPH_BASE + 0x00006000)
/*
* Address of the SCU_SFS register for the given pin
*/
#define LPC18XX_PIN_REG_ADDR(group,pin) \
(LPC18XX_SCU_BASE + (group) * 0x80 + (pin) * 4)
/*
* Reference to the SCU_SFS register for the given pin