Commit 6a2c27cd authored by Alexander Potashev's avatar Alexander Potashev

RT77744. lpc4350-eval: Configure EMC for SDRAM

 * Use M4_CLK/2 = 102MHz for SDRAM clock;
 * Use best-performance timings for SDRAM.
parent e5bf9585
This diff is collapsed.
......@@ -34,6 +34,14 @@ DECLARE_GLOBAL_DATA_PTR;
/* Maximum number of pins in each group */
#define LPC18XX_IOMUX_GROUP_PINS 32
/*
* Pins CLK0..CLK3 with imaginary numbers 0x18.0-0x18.3
*/
/* Index of the the imaginary group of pins */
#define LPC18XX_IOMUX_CLK_GROUP 24
/* Number of CLK0..CLK3 pins */
#define LPC18XX_IOMUX_CLK_PINS 4
/*
* System Control Unit (SCU) registers base
*/
......@@ -59,8 +67,11 @@ static inline int lpc18xx_validate_pin(const struct lpc18xx_iomux_dsc *dsc)
rv = 0;
if (!dsc || dsc->group >= LPC18XX_IOMUX_GROUPS ||
dsc->pin >= LPC18XX_IOMUX_GROUP_PINS) {
if (!dsc ||
((dsc->group >= LPC18XX_IOMUX_GROUPS ||
dsc->pin >= LPC18XX_IOMUX_GROUP_PINS) &&
(dsc->group != LPC18XX_IOMUX_CLK_GROUP ||
dsc->pin >= LPC18XX_IOMUX_CLK_PINS))) {
if (gd->have_console) {
printf("IOMUX: incorrect params %d.%d.\n",
dsc ? dsc->group : -1,
......
/*
* (C) Copyright 2012
*
* Alexander Potashev, Emcraft Systems, aspotashev@emcraft.com
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _MACH_CCU_H_
#define _MACH_CCU_H_
/*
* CCU1 (Clock Control Unit 1) register map
*/
struct lpc18xx_ccu1_regs {
u32 pm; /* CCU1 power mode register */
u32 base_stat; /* CCU1 base clock status register */
u32 rsv0[62];
u32 clk_apb3_bus_cfg; /* CLK_APB3_BUS clock configuration */
u32 clk_apb3_bus_stat; /* CLK_APB3_BUS clock status */
u32 clk_apb3_i2c1_cfg; /* CLK_APB3_I2C1 configuration */
u32 clk_apb3_i2c1_stat; /* CLK_APB3_I2C1 status */
u32 clk_apb3_dac_cfg; /* CLK_APB3_DAC configuration */
u32 clk_apb3_dac_stat; /* CLK_APB3_DAC status */
u32 clk_apb3_adc0_cfg; /* CLK_APB3_ADC0 configuration */
u32 clk_apb3_adc0_stat; /* CLK_APB3_ADC0 status */
u32 clk_apb3_adc1_cfg; /* CLK_APB3_ADC1 configuration */
u32 clk_apb3_adc1_stat; /* CLK_APB3_ADC1 status */
u32 clk_apb3_can0_cfg; /* CLK_APB3_CAN0 configuration */
u32 clk_apb3_can0_stat; /* CLK_APB3_CAN0 status */
u32 rsv1[52];
u32 clk_apb1_bus_cfg; /* CLK_APB1_BUS configuration */
u32 clk_apb1_bus_stat; /* CLK_APB1_BUS status */
u32 clk_apb1_motocon_cfg; /* CLK_APB1_MOTOCON configuration */
u32 clk_apb1_motocon_stat; /* CLK_APB1_MOTOCON status */
u32 clk_apb1_i2c0_cfg; /* CLK_APB1_I2C0 configuration */
u32 clk_apb1_i2c0_stat; /* CLK_APB1_I2C0 status */
u32 clk_apb1_i2s_cfg; /* CLK_APB1_I2S configuration */
u32 clk_apb1_i2s_stat; /* CLK_APB1_I2S status */
u32 clk_apb1_can1_cfg; /* CLK_APB3_CAN1 configuration */
u32 clk_apb1_can1_stat; /* CLK_APB3_CAN1 status */
u32 rsv2[54];
u32 clk_spifi_cfg; /* CLK_SPIFI configuration */
u32 clk_spifi_stat; /* CLK_SPIFI status */
u32 rsv3[62];
u32 clk_m4_bus_cfg; /* CLK_M4_BUS configuration */
u32 clk_m4_bus_stat; /* CLK_M4_BUS status */
u32 clk_m4_spifi_cfg; /* CLK_M4_SPIFI configuration */
u32 clk_m4_spifi_stat; /* CLK_M4_SPIFI status */
u32 clk_m4_gpio_cfg; /* CLK_M4_GPIO configuration */
u32 clk_m4_gpio_stat; /* CLK_M4_GPIO status */
u32 clk_m4_lcd_cfg; /* CLK_M4_LCD configuration */
u32 clk_m4_lcd_stat; /* CLK_M4_LCD status */
u32 clk_m4_ethernet_cfg; /* CLK_M4_ETHERNET configuration */
u32 clk_m4_ethernet_stat; /* CLK_M4_ETHERNET status */
u32 clk_m4_usb0_cfg; /* CLK_M4_USB0 configuration */
u32 clk_m4_usb0_stat; /* CLK_M4_USB0 status */
u32 clk_m4_emc_cfg; /* CLK_M4_EMC configuration */
u32 clk_m4_emc_stat; /* CLK_M4_EMC status */
u32 clk_m4_sdio_cfg; /* CLK_M4_SDIO configuration */
u32 clk_m4_sdio_stat; /* CLK_M4_SDIO status */
u32 clk_m4_dma_cfg; /* CLK_M4_DMA configuration */
u32 clk_m4_dma_stat; /* CLK_M4_DMA status */
u32 clk_m4_m4core_cfg; /* CLK_M4_M4CORE configuration */
u32 clk_m4_m4core_stat; /* CLK_M4_M4CORE status */
u32 rsv4[6];
u32 clk_m4_sct_cfg; /* CLK_M4_SCT configuration */
u32 clk_m4_sct_stat; /* CLK_M4_SCT status */
u32 clk_m4_usb1_cfg; /* CLK_M4_USB1 configuration */
u32 clk_m4_usb1_stat; /* CLK_M4_USB1 status */
u32 clk_m4_emcdiv_cfg; /* CLK_M4_EMCDIV configuration */
u32 clk_m4_emcdiv_stat; /* CLK_M4_EMCDIV status */
u32 rsv5[4];
u32 clk_m4_m0app_cfg; /* CLK_M4_M0_CFG configuration */
u32 clk_m4_m0app_stat; /* CLK_M4_M0_STAT status */
u32 clk_m4_vadc_cfg; /* CLK_M4_VADC_CFG configuration */
u32 clk_m4_vadc_stat; /* CLK_M4_VADC_STAT configuration */
u32 rsv6[24];
u32 clk_m4_wwdt_cfg; /* CLK_M4_WWDT configuration */
u32 clk_m4_wwdt_stat; /* CLK_M4_WWDT status */
u32 clk_m4_usart0_cfg; /* CLK_M4_UART0 configuration */
u32 clk_m4_usart0_stat; /* CLK_M4_UART0 status */
u32 clk_m4_uart1_cfg; /* CLK_M4_UART1 configuration */
u32 clk_m4_uart1_stat; /* CLK_M4_UART1 status */
u32 clk_m4_ssp0_cfg; /* CLK_M4_SSP0 configuration */
u32 clk_m4_ssp0_stat; /* CLK_M4_SSP0 status */
u32 clk_m4_timer0_cfg; /* CLK_M4_TIMER0 configuration */
u32 clk_m4_timer0_stat; /* CLK_M4_TIMER0 status */
u32 clk_m4_timer1_cfg; /* CLK_M4_TIMER1 configuration */
u32 clk_m4_timer1_stat; /* CLK_M4_TIMER1 status */
u32 clk_m4_scu_cfg; /* CLK_M4_SCU configuration */
u32 clk_m4_scu_stat; /* CLK_M4_SCU status */
u32 clk_m4_creg_cfg; /* CLK_M4_CREG configuration */
u32 clk_m4_creg_stat; /* CLK_M4_CREG status */
u32 rsv7[48];
u32 clk_m4_ritimer_cfg; /* CLK_M4_RITIMER configuration */
u32 clk_m4_ritimer_stat; /* CLK_M4_RITIMER status */
u32 clk_m4_usart2_cfg; /* CLK_M4_UART2 configuration */
u32 clk_m4_usart2_stat; /* CLK_M4_UART2 status */
u32 clk_m4_usart3_cfg; /* CLK_M4_UART3 configuration */
u32 clk_m4_usart3_stat; /* CLK_M4_UART3 status */
u32 clk_m4_timer2_cfg; /* CLK_M4_TIMER2 configuration */
u32 clk_m4_timer2_stat; /* CLK_M4_TIMER2 status */
u32 clk_m4_timer3_cfg; /* CLK_M4_TIMER3 configuration */
u32 clk_m4_timer3_stat; /* CLK_M4_TIMER3 status */
u32 clk_m4_ssp1_cfg; /* CLK_M4_SSP1 configuration */
u32 clk_m4_ssp1_stat; /* CLK_M4_SSP1 status */
u32 clk_m4_qei_cfg; /* CLK_M4_QEI configuration */
u32 clk_m4_qei_stat; /* CLK_M4_QEI status */
u32 rsv8[50];
u32 clk_periph_bus_cfg; /* CLK_PERIPH_BUS configuration */
u32 clk_periph_bus_stat; /* CLK_PERIPH_BUS status */
u32 rsv9[2];
u32 clk_periph_core_cfg; /* CLK_PERIPH_CORE configuration */
u32 clk_periph_core_stat; /* CLK_PERIPH_CORE status */
u32 clk_periph_sgpio_cfg; /* CLK_PERIPH_SGPIO configuration */
u32 clk_periph_sgpio_stat; /* CLK_PERIPH_SGPIO status */
u32 rsv10[56];
u32 clk_usb0_cfg; /* CLK_USB0 configuration */
u32 clk_usb0_stat; /* CLK_USB0 status */
u32 rsv11[62];
u32 clk_usb1_cfg; /* CLK_USB1 configuration */
u32 clk_usb1_stat; /* CLK_USB1 status */
u32 rsv12[62];
u32 clk_spi_cfg; /* CLK_SPI configuration */
u32 clk_spi_stat; /* CLK_SPI status */
u32 rsv13[62];
u32 clk_vadc_cfg; /* CLK_VADC configuration */
u32 clk_vadc_stat; /* CLK_VADC status */
};
/*
* CCU1 registers base
*/
#define LPC18XX_CCU1_BASE 0x40051000
#define LPC18XX_CCU1 ((volatile struct lpc18xx_ccu1_regs *) \
LPC18XX_CCU1_BASE)
/*
* All clock configuration registers
*/
#define LPC18XX_CCU1_CLK_RUN_MSK (1 << 0)
/*
* CLK_M4_EMCDIV_CFG register
*/
/* Divider selector */
#define LPC18XX_CCU1_CLK_EMCDIV_CFG_DIV2 (1 << 5)
#endif /* _MACH_CCU_H_ */
/*
* (C) Copyright 2012
*
* Alexander Potashev, Emcraft Systems, aspotashev@emcraft.com
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _MACH_CREG_H_
#define _MACH_CREG_H_
/*
* CREG (Configuration Registers) register map
*/
struct lpc18xx_creg_regs {
u32 rsv0;
u32 creg0; /* Chip configuration register 0 */
u32 rsv1[62];
u32 m4memmap; /* ARM Cortex-M4 memory mapping */
u32 rsv2;
u32 creg1; /* Chip configuration register 1 */
u32 creg2; /* Chip configuration register 2 */
u32 creg3; /* Chip configuration register 3 */
u32 creg4; /* Chip configuration register 4 */
u32 creg5; /* Chip configuration register 5 */
u32 dmamux; /* DMA muxing control */
u32 rsv3[2];
u32 etbcfg; /* ETB RAM configuration */
u32 creg6; /* Chip configuration register 6 */
u32 m4txevent; /* Cortex-M4 TXEV event clear */
u32 rsv4[51];
u32 chipid; /* Part ID */
u32 rsv5[127];
u32 m0txevent; /* Cortex-M0 TXEV event clear */
u32 m0appmemmap; /* ARM Cortex-M0 memory mapping */
};
/*
* CREG registers base
*/
#define LPC18XX_CREG_BASE 0x40043000
#define LPC18XX_CREG ((volatile struct lpc18xx_creg_regs *) \
LPC18XX_CREG_BASE)
/*
* CREG6 register
*/
/* Selects the Ethernet mode */
#define LPC18XX_CREG_CREG6_ETHMODE_BITS 0
#define LPC18XX_CREG_CREG6_ETHMODE_MSK \
(7 << LPC18XX_CREG_CREG6_ETHMODE_BITS)
#define LPC18XX_CREG_CREG6_ETHMODE_MII \
(0 << LPC18XX_CREG_CREG6_ETHMODE_BITS)
/* EMC_CLK divided clock select */
#define LPC18XX_CREG_CREG6_EMCCLKSEL_MSK (1 << 16)
#endif /* _MACH_CREG_H_ */
/*
* (C) Copyright 2012
*
* Alexander Potashev, Emcraft Systems, aspotashev@emcraft.com
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _MACH_SCU_H_
#define _MACH_SCU_H_
/*
* SCU (System Control Unit) register map
*/
struct lpc18xx_scu_regs {
u32 sfs[802]; /* Pin configuration registers */
u32 enaio0; /* ADC0 function select register */
u32 enaio1; /* ADC1 function select register */
u32 enaio2; /* Analog function select register */
u32 rsv0[27];
u32 emcdelayclk; /* EMC clock delay register */
u32 rsv1[63];
u32 pintsel0; /* Pin interrupt select for interrupts 0 to 3 */
u32 pintsel1; /* Pin interrupt select for interrupts 4 to 7 */
};
/*
* SCU registers base
*/
#define LPC18XX_SCU_BASE 0x40086000
#define LPC18XX_SCU ((volatile struct lpc18xx_scu_regs *) \
LPC18XX_SCU_BASE)
#endif /* _MACH_SCU_H_ */
......@@ -131,6 +131,10 @@
#define CONFIG_SYS_RAM_CS 0 /* 0 .. 3 */
#define CONFIG_SYS_RAM_BASE 0x28000000
#define CONFIG_SYS_RAM_SIZE (8 * 1024 * 1024)
/*
* Use the CPU_CLOCK/2 for EMC
*/
#define CONFIG_LPC18XX_EMC_HALFCPU
/*
* Store env in memory only, if no flash.
......
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