Commit 6a2c27cd authored by Alexander Potashev's avatar Alexander Potashev

RT77744. lpc4350-eval: Configure EMC for SDRAM

 * Use M4_CLK/2 = 102MHz for SDRAM clock;
 * Use best-performance timings for SDRAM.
parent e5bf9585
......@@ -27,6 +27,222 @@
#include <netdev.h>
#include <asm/arch/lpc18xx_gpio.h>
#include <asm/arch/lpc18xx_scu.h>
#include <asm/arch/lpc18xx_creg.h>
#include <asm/arch/lpc18xx_ccu.h>
/*
* IS42S16400F SDRAM: 16-bit, 4 banks, 12 row bits, 8 column bits.
* See table 364 "Address mapping" on page 417 in the LPC43xx User Manual.
*/
#define LPC18XX_EMC_AM 0x05
/*
* Timings for 102 MHz SDRAM clock and IS42S16400F-6TL memory chip
*/
/* Active to read/write delay (RAS latency) */
#define SDRAM_RAS 2 /* tRCD = 18ns */
/* CAS latency (CL) */
#define SDRAM_CAS 2 /* CL = 2 */
/* Command delayed strategy, using EMCCLKDELAY */
#define SDRAM_RDCFG_RD 1
/* Precharge command period (tRP) */
#define SDRAM_T_RP 2 /* 18ns */
/* Active to precharge command perion (tRAS) */
#define SDRAM_T_RAS 5 /* 42ns */
/* Self-refresh exit time (tSREX) */
#define SDRAM_T_SREX 7 /* We set this to the same as tXSR */
/* Last-data-out to active command time (tAPR) */
#define SDRAM_T_APR 6 /* Not found in the SDRAM datasheet */
/* Data-in to active command (tDAL) */
#define SDRAM_T_DAL 5 /* 5 cycles */
/* Write recovery time (tWR) */
#define SDRAM_T_WR 2 /* 2 cycles */
/* Active to active command perion (tRC) */
#define SDRAM_T_RC 7 /* 60ns */
/* Auto-refresh period and auto-refresh to active command period (tRFC) */
#define SDRAM_T_RFC 7 /* 60ns */
/* Exit self-refresh to active command time (tXSR) */
#define SDRAM_T_XSR 7 /* 60ns */
/* Active bank A to active bank B latency (tRRD) */
#define SDRAM_T_RRD 2 /* 12ns */
/* Load mode register to active command time (tMRD) */
#define SDRAM_T_MRD 2 /* 2 cycles */
/*
* Refresh timer.
* Indicates the multiple of 16 CCLKs between SDRAM refresh cycles.
*/
/* 99 = 64000000[64ms] / 4096[rows] / 9.80[ns] / 16; round down */
#define SDRAM_REFRESH 99
/* Only for initialization */
#define SDRAM_REFRESH_FAST 1
/*
* EMC registers
*/
/*
* EMC Control register
*/
#define LPC_EMC_CTRL_EN_MSK (1 << 0)
/*
* Dynamic Memory Control register
*/
/* Dynamic memory clock enable (CE) */
#define LPC_EMC_DYCTRL_CE_MSK (1 << 0)
/* Dynamic memory clock control (CS) */
#define LPC_EMC_DYCTRL_CS_MSK (1 << 1)
/* SDRAM initialization (I) */
#define LPC_EMC_DYCTRL_I_BITS 7
#define LPC_EMC_DYCTRL_I_NORMAL 0
#define LPC_EMC_DYCTRL_I_MODE 1
#define LPC_EMC_DYCTRL_I_PALL 2 /* precharge all */
#define LPC_EMC_DYCTRL_I_NOP 3 /* no operation */
/*
* Dynamic Memory Read Configuration register:
* Read data strategy (RD)
*/
#define LPC_EMC_DYRDCFG_RD_BITS 0
/*
* The SDRAM chip (IS42S16400F) mode register.
* See IS42S16400F datasheet, page 16.
*/
#define SDRAM_MODEREG_BL_BITS 0 /* Burst Length */
#define SDRAM_MODEREG_CAS_BITS 4 /* CAS Latency */
/*
* See IS42S16400F mode register (IS42S16400F datasheet, page 16).
* CAS3, Burst Length = 8.
*/
#define SDRAM_MODEREG_BL 3 /* Burst Length code */
#define SDRAM_MODEREG_CAS 2 /* CAS Latency */
#define SDRAM_MODEREG_VALUE \
((SDRAM_MODEREG_BL << SDRAM_MODEREG_BL_BITS) | \
(SDRAM_MODEREG_CAS << SDRAM_MODEREG_CAS_BITS))
/*
* SDRAM chip-specific options
*/
/*
* Offset of the 12 least-significant bits of mode register (A0..A11)
* in addresses on the AHB bus.
*
* In the high-performance mode the shift should be the following:
* 11 = 8 (column bits) + 2 (bank select bits) + 1 (16 bits)
* 1. IS42S32800B SDRAM has 256 columns, therefore 8 bits are used
* for the column number.
* 2. Bank select field has 2 bits (4 banks).
* 3. `1` is log2(16/8), because the SDRAM chip is 16-bit, and its
* internal addresses do not have 1 least-significant bit of
* the AHB bus addresses.
*
* In the low-power mode this shift will be different.
*/
#define LPC18XX_EMC_MODEREG_ADDR_SHIFT 11
/*
* Dynamic Memory registers (per chip)
*/
/*
* Dynamic Memory Configuration register
*/
/* Address mapping */
#define LPC_EMC_DYCFG_AM_BITS 7
/* Buffer enable */
#define LPC_EMC_DYCFG_B_MSK (1 << 19)
/*
* Dynamic Memory RAS & CAS Delay register
*/
/* RAS latency */
#define LPC_EMC_DYRASCAS_RAS_BITS 0
/* CAS latency */
#define LPC_EMC_DYRASCAS_CAS_BITS 8
/*
* EMC per-chip registers for DRAM.
*
* This structure must be 0x20 bytes in size
* (for `struct lpc_emc_regs` to be correct.)
*/
struct lpc_emc_dy_regs {
u32 cfg; /* Dynamic Memory Configuration register */
u32 rascas; /* Dynamic Memory RAS & CAS Delay registers */
u32 rsv0[6];
};
/*
* EMC controls for Static Memory CS. Each block occupies 0x20 bytes.
*/
struct lpc_emc_st_regs {
u32 cfg; /* Static Memory Configuration register */
u32 we; /* CS to WE delay register */
u32 oe; /* CS to OE delay register */
u32 rd; /* CS to Read delay register */
u32 page; /* async page mode access delay */
u32 wr; /* CS to Write delay register */
u32 ta; /* number of turnaround cycles */
u32 rsv0[1];
};
/*
* EMC (External Memory Controller) register map
*/
struct lpc_emc_regs {
/* 0x000 */
u32 emcctrl; /* EMC Control register */
u32 emcsts; /* EMC Status register */
u32 emccfg; /* EMC Configuration register */
u32 rsv0[5];
/* 0x020 */
u32 dy_ctrl; /* Dynamic Memory Control register */
u32 dy_rfsh; /* Dynamic Memory Refresh Timer register */
u32 dy_rdcfg; /* Dynamic Memory Read Configuration register */
u32 rsv1;
/* 0x030 */
u32 dy_trp; /* Dynamic Memory Precharge Command Period register */
u32 dy_tras; /* Dynamic Memory Active to Precharge Command
Period register */
u32 dy_srex; /* Dynamic Memory Self-refresh Exit Time register */
u32 dy_apr; /* Dynamic Memory Last Data Out to Active
Time register */
u32 dy_dal; /* Dynamic Memory Data-in to Active Command
Time register */
u32 dy_wr; /* Dynamic Memory Write Recovery Time register */
u32 dy_rc; /* Dynamic Memory Active to Active Command
Period register */
u32 dy_rfc; /* Dynamic Memory Auto-refresh Period register */
u32 dy_xsr; /* Dynamic Memory Exit Self-refresh register */
u32 dy_rrd; /* Dynamic Memory Active Bank A to
Active Bank B Time register */
u32 dy_mrd; /* Dynamic Memory Load Mode register to
Active Command Time */
/* 0x05C */
u32 rsv2[41];
/* 0x100 */
struct lpc_emc_dy_regs dy[4]; /* 4 DRAM chips are possible */
u32 rsv3[32];
/* 0x200 */
struct lpc_emc_st_regs st[4]; /* 4 static memory devices */
};
#define LPC18XX_EMC_BASE 0x40005000
#define LPC_EMC ((volatile struct lpc_emc_regs *) \
LPC18XX_EMC_BASE)
DECLARE_GLOBAL_DATA_PTR;
/*
* Pin settings for EMC pins
*/
#define LPC18XX_IOMUX_EMC_CONFIG(func) \
(LPC18XX_IOMUX_CONFIG(func, 0, 1, 1, 1, 1))
/*
* Pin configuration table for Hitex LPC4350 Eval.
......@@ -42,6 +258,110 @@ static const struct lpc18xx_pin_config hitex_lpc4350_iomux[] = {
LPC18XX_IOMUX_CONFIG(1, 0, 1, 0, 0, 0)},
{{CONFIG_LPC18XX_UART_RX_IO_GROUP, CONFIG_LPC18XX_UART_RX_IO_PIN},
LPC18XX_IOMUX_CONFIG(1, 0, 1, 0, 1, 0)},
#if defined(CONFIG_NR_DRAM_BANKS) || defined(CONFIG_SYS_FLASH_CS)
/*
* EMC pins used for both the SDRAM and the NOR flash memory chips
*/
/* P1.6 = WE# - SDRAM,NOR */
{{0x1, 6}, LPC18XX_IOMUX_EMC_CONFIG(3)},
/* P2.10 = A1 - SDRAM,NOR */
{{0x2, 10}, LPC18XX_IOMUX_EMC_CONFIG(3)},
/* P2.11 = A2 - SDRAM,NOR */
{{0x2, 11}, LPC18XX_IOMUX_EMC_CONFIG(3)},
/* P2.12 = A3 - SDRAM,NOR */
{{0x2, 12}, LPC18XX_IOMUX_EMC_CONFIG(3)},
/* P2.13 = A4 - SDRAM,NOR */
{{0x2, 13}, LPC18XX_IOMUX_EMC_CONFIG(3)},
/* P1.0 = A5 - SDRAM,NOR */
{{0x1, 0}, LPC18XX_IOMUX_EMC_CONFIG(2)},
/* P1.1 = A6 - SDRAM,NOR */
{{0x1, 1}, LPC18XX_IOMUX_EMC_CONFIG(2)},
/* P1.2 = A7 - SDRAM,NOR */
{{0x1, 2}, LPC18XX_IOMUX_EMC_CONFIG(2)},
/* P2.8 = A8 - SDRAM,NOR */
{{0x2, 8}, LPC18XX_IOMUX_EMC_CONFIG(3)},
/* P2.7 = A9 - SDRAM,NOR */
{{0x2, 7}, LPC18XX_IOMUX_EMC_CONFIG(3)},
/* P2.6 = A10 - SDRAM,NOR */
{{0x2, 6}, LPC18XX_IOMUX_EMC_CONFIG(2)},
/* P2.2 = A11 - SDRAM,NOR */
{{0x2, 2}, LPC18XX_IOMUX_EMC_CONFIG(2)},
/* P2.0 = BA0 for SDRAM (aka A13) - SDRAM,NOR */
{{0x2, 0}, LPC18XX_IOMUX_EMC_CONFIG(2)},
/* P6.8 = BA1 for SDRAM (aka A14) - SDRAM,NOR */
{{0x6, 8}, LPC18XX_IOMUX_EMC_CONFIG(1)},
/* P1.7 = D0 - SDRAM,NOR */
{{0x1, 7}, LPC18XX_IOMUX_EMC_CONFIG(3)},
/* P1.8 = D1 - SDRAM,NOR */
{{0x1, 8}, LPC18XX_IOMUX_EMC_CONFIG(3)},
/* P1.9 = D2 - SDRAM,NOR */
{{0x1, 9}, LPC18XX_IOMUX_EMC_CONFIG(3)},
/* P1.10 = D3 - SDRAM,NOR */
{{0x1, 10}, LPC18XX_IOMUX_EMC_CONFIG(3)},
/* P1.11 = D4 - SDRAM,NOR */
{{0x1, 11}, LPC18XX_IOMUX_EMC_CONFIG(3)},
/* P1.12 = D5 - SDRAM,NOR */
{{0x1, 12}, LPC18XX_IOMUX_EMC_CONFIG(3)},
/* P1.13 = D6 - SDRAM,NOR */
{{0x1, 13}, LPC18XX_IOMUX_EMC_CONFIG(3)},
/* P1.14 = D7 - SDRAM,NOR */
{{0x1, 14}, LPC18XX_IOMUX_EMC_CONFIG(3)},
/* P5.4 = D8 - SDRAM,NOR */
{{0x5, 4}, LPC18XX_IOMUX_EMC_CONFIG(2)},
/* P5.5 = D9 - SDRAM,NOR */
{{0x5, 5}, LPC18XX_IOMUX_EMC_CONFIG(2)},
/* P5.6 = D10 - SDRAM,NOR */
{{0x5, 6}, LPC18XX_IOMUX_EMC_CONFIG(2)},
/* P5.7 = D11 - SDRAM,NOR */
{{0x5, 7}, LPC18XX_IOMUX_EMC_CONFIG(2)},
/* P5.0 = D12 - SDRAM,NOR */
{{0x5, 0}, LPC18XX_IOMUX_EMC_CONFIG(2)},
/* P5.1 = D13 - SDRAM,NOR */
{{0x5, 1}, LPC18XX_IOMUX_EMC_CONFIG(2)},
/* P5.2 = D14 - SDRAM,NOR */
{{0x5, 2}, LPC18XX_IOMUX_EMC_CONFIG(2)},
/* P5.3 = D15 - SDRAM,NOR */
{{0x5, 3}, LPC18XX_IOMUX_EMC_CONFIG(2)},
#endif /* CONFIG_NR_DRAM_BANKS || CONFIG_SYS_FLASH_CS */
#if defined(CONFIG_NR_DRAM_BANKS)
/*
* Configuration for EMC pins used only for SDRAM
*/
/*
* To use 16-bit wide and 32-bit wide SDRAM interfaces, select
* the EMC_CLK function and enable the input buffer (EZI = 1)
* in all four SFSCLKn registers in the SCU.
*/
/* Imaginary P-0x18.0 = CLK (CLK0) - SDRAM */
{{0x18, 0}, LPC18XX_IOMUX_EMC_CONFIG(0)},
/* Imaginary P-0x18.1 = CLK1 - SDRAM */
{{0x18, 1}, LPC18XX_IOMUX_EMC_CONFIG(0)},
/* Imaginary P-0x18.2 = CLK2 - SDRAM */
{{0x18, 2}, LPC18XX_IOMUX_EMC_CONFIG(0)},
/* Imaginary P-0x18.3 = CLK3 - SDRAM */
{{0x18, 3}, LPC18XX_IOMUX_EMC_CONFIG(0)},
/* P6.11 = CKE - SDRAM */
{{0x6, 11}, LPC18XX_IOMUX_EMC_CONFIG(3)},
/* P6.9 = CS# (nDYCS0) - SDRAM */
{{0x6, 9}, LPC18XX_IOMUX_EMC_CONFIG(3)},
/* P6.5 = RAS# - SDRAM */
{{0x6, 5}, LPC18XX_IOMUX_EMC_CONFIG(3)},
/* P6.4 = CAS# - SDRAM */
{{0x6, 4}, LPC18XX_IOMUX_EMC_CONFIG(3)},
/* P6.12 = DQM0 - SDRAM */
{{0x6, 12}, LPC18XX_IOMUX_EMC_CONFIG(3)},
/* P6.10 = DQM1 - SDRAM */
{{0x6, 10}, LPC18XX_IOMUX_EMC_CONFIG(3)},
/* P2.9 = A0 - SDRAM */
{{0x2, 9}, LPC18XX_IOMUX_EMC_CONFIG(3)},
#endif /* CONFIG_NR_DRAM_BANKS */
};
/*
......@@ -61,6 +381,20 @@ static void iomux_init(void)
*/
int board_init(void)
{
/*
* Set SDRAM clock output delay to ~3.5ns (0x7777),
* the SDRAM chip does not work otherwise.
*/
LPC18XX_SCU->emcdelayclk = 0x7777;
/*
* Enable EMC
*/
LPC_EMC->emcctrl = LPC_EMC_CTRL_EN_MSK;
/*
* Little-endian mode
*/
LPC_EMC->emccfg = 0;
/*
* Configure MCU pins
*/
......@@ -91,10 +425,105 @@ int misc_init_r(void)
}
#endif /* CONFIG_MISC_INIT_R */
#define mdelay(n) ({unsigned long msec=(n); while (msec--) udelay(1000);})
/*
* Setup external RAM.
*/
int dram_init(void)
{
volatile struct lpc_emc_dy_regs *dy;
u32 tmp32;
#ifdef CONFIG_LPC18XX_EMC_HALFCPU
/*
* EMC_CLK_DIV = M4_CLK / 2
*/
LPC18XX_CCU1->clk_m4_emcdiv_cfg |=
LPC18XX_CCU1_CLK_RUN_MSK | LPC18XX_CCU1_CLK_EMCDIV_CFG_DIV2;
LPC18XX_CREG->creg6 |= LPC18XX_CREG_CREG6_EMCCLKSEL_MSK;
LPC18XX_CCU1->clk_m4_emc_cfg |= LPC18XX_CCU1_CLK_RUN_MSK;
#else
#error EMC clock set to M4_CLK/1 is not supported
#endif
dy = &LPC_EMC->dy[CONFIG_SYS_RAM_CS];
/*
* Address mapping
*/
dy->cfg = (LPC18XX_EMC_AM << LPC_EMC_DYCFG_AM_BITS);
/*
* Configure DRAM timing
*/
dy->rascas =
(SDRAM_RAS << LPC_EMC_DYRASCAS_RAS_BITS) |
(SDRAM_CAS << LPC_EMC_DYRASCAS_CAS_BITS);
LPC_EMC->dy_rdcfg =
(SDRAM_RDCFG_RD << LPC_EMC_DYRDCFG_RD_BITS);
LPC_EMC->dy_trp = SDRAM_T_RP - 1;
LPC_EMC->dy_tras = SDRAM_T_RAS - 1;
LPC_EMC->dy_srex = SDRAM_T_SREX - 1;
LPC_EMC->dy_apr = SDRAM_T_APR - 1;
LPC_EMC->dy_dal = SDRAM_T_DAL;
LPC_EMC->dy_wr = SDRAM_T_WR - 1;
LPC_EMC->dy_rc = SDRAM_T_RC - 1;
LPC_EMC->dy_rfc = SDRAM_T_RFC - 1;
LPC_EMC->dy_xsr = SDRAM_T_XSR - 1;
LPC_EMC->dy_rrd = SDRAM_T_RRD - 1;
LPC_EMC->dy_mrd = SDRAM_T_MRD - 1;
mdelay(100);
/*
* Issue SDRAM NOP (no operation) command
*/
LPC_EMC->dy_ctrl =
LPC_EMC_DYCTRL_CE_MSK | LPC_EMC_DYCTRL_CS_MSK |
(LPC_EMC_DYCTRL_I_NOP << LPC_EMC_DYCTRL_I_BITS);
mdelay(200);
/*
* Pre-charge all with fast refresh
*/
LPC_EMC->dy_ctrl =
LPC_EMC_DYCTRL_CE_MSK | LPC_EMC_DYCTRL_CS_MSK |
(LPC_EMC_DYCTRL_I_PALL << LPC_EMC_DYCTRL_I_BITS);
LPC_EMC->dy_rfsh = SDRAM_REFRESH_FAST;
mdelay(1);
/*
* Set refresh period
*/
LPC_EMC->dy_rfsh = SDRAM_REFRESH;
/*
* Load mode register
*/
LPC_EMC->dy_ctrl =
LPC_EMC_DYCTRL_CE_MSK | LPC_EMC_DYCTRL_CS_MSK |
(LPC_EMC_DYCTRL_I_MODE << LPC_EMC_DYCTRL_I_BITS);
tmp32 = *(volatile u32 *)(CONFIG_SYS_RAM_BASE |
(SDRAM_MODEREG_VALUE << LPC18XX_EMC_MODEREG_ADDR_SHIFT));
/*
* Normal mode
*/
LPC_EMC->dy_ctrl =
(LPC_EMC_DYCTRL_I_NORMAL << LPC_EMC_DYCTRL_I_BITS);
/*
* Enable DRAM buffer
*/
dy->cfg = (LPC18XX_EMC_AM << LPC_EMC_DYCFG_AM_BITS) |
LPC_EMC_DYCFG_B_MSK;
/*
* Fill in global info with description of DRAM configuration
*/
gd->bd->bi_dram[0].start = CONFIG_SYS_RAM_BASE;
gd->bd->bi_dram[0].size = CONFIG_SYS_RAM_SIZE;
return 0;
}
......@@ -34,6 +34,14 @@ DECLARE_GLOBAL_DATA_PTR;
/* Maximum number of pins in each group */
#define LPC18XX_IOMUX_GROUP_PINS 32
/*
* Pins CLK0..CLK3 with imaginary numbers 0x18.0-0x18.3
*/
/* Index of the the imaginary group of pins */
#define LPC18XX_IOMUX_CLK_GROUP 24
/* Number of CLK0..CLK3 pins */
#define LPC18XX_IOMUX_CLK_PINS 4
/*
* System Control Unit (SCU) registers base
*/
......@@ -59,8 +67,11 @@ static inline int lpc18xx_validate_pin(const struct lpc18xx_iomux_dsc *dsc)
rv = 0;
if (!dsc || dsc->group >= LPC18XX_IOMUX_GROUPS ||
dsc->pin >= LPC18XX_IOMUX_GROUP_PINS) {
if (!dsc ||
((dsc->group >= LPC18XX_IOMUX_GROUPS ||
dsc->pin >= LPC18XX_IOMUX_GROUP_PINS) &&
(dsc->group != LPC18XX_IOMUX_CLK_GROUP ||
dsc->pin >= LPC18XX_IOMUX_CLK_PINS))) {
if (gd->have_console) {
printf("IOMUX: incorrect params %d.%d.\n",
dsc ? dsc->group : -1,
......
/*
* (C) Copyright 2012
*
* Alexander Potashev, Emcraft Systems, aspotashev@emcraft.com
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _MACH_CCU_H_
#define _MACH_CCU_H_
/*
* CCU1 (Clock Control Unit 1) register map
*/
struct lpc18xx_ccu1_regs {
u32 pm; /* CCU1 power mode register */
u32 base_stat; /* CCU1 base clock status register */
u32 rsv0[62];
u32 clk_apb3_bus_cfg; /* CLK_APB3_BUS clock configuration */
u32 clk_apb3_bus_stat; /* CLK_APB3_BUS clock status */
u32 clk_apb3_i2c1_cfg; /* CLK_APB3_I2C1 configuration */
u32 clk_apb3_i2c1_stat; /* CLK_APB3_I2C1 status */
u32 clk_apb3_dac_cfg; /* CLK_APB3_DAC configuration */
u32 clk_apb3_dac_stat; /* CLK_APB3_DAC status */
u32 clk_apb3_adc0_cfg; /* CLK_APB3_ADC0 configuration */
u32 clk_apb3_adc0_stat; /* CLK_APB3_ADC0 status */
u32 clk_apb3_adc1_cfg; /* CLK_APB3_ADC1 configuration */
u32 clk_apb3_adc1_stat; /* CLK_APB3_ADC1 status */
u32 clk_apb3_can0_cfg; /* CLK_APB3_CAN0 configuration */
u32 clk_apb3_can0_stat; /* CLK_APB3_CAN0 status */
u32 rsv1[52];
u32 clk_apb1_bus_cfg; /* CLK_APB1_BUS configuration */
u32 clk_apb1_bus_stat; /* CLK_APB1_BUS status */
u32 clk_apb1_motocon_cfg; /* CLK_APB1_MOTOCON configuration */
u32 clk_apb1_motocon_stat; /* CLK_APB1_MOTOCON status */
u32 clk_apb1_i2c0_cfg; /* CLK_APB1_I2C0 configuration */
u32 clk_apb1_i2c0_stat; /* CLK_APB1_I2C0 status */
u32 clk_apb1_i2s_cfg; /* CLK_APB1_I2S configuration */
u32 clk_apb1_i2s_stat; /* CLK_APB1_I2S status */
u32 clk_apb1_can1_cfg; /* CLK_APB3_CAN1 configuration */
u32 clk_apb1_can1_stat; /* CLK_APB3_CAN1 status */
u32 rsv2[54];
u32 clk_spifi_cfg; /* CLK_SPIFI configuration */
u32 clk_spifi_stat; /* CLK_SPIFI status */
u32 rsv3[62];
u32 clk_m4_bus_cfg; /* CLK_M4_BUS configuration */
u32 clk_m4_bus_stat; /* CLK_M4_BUS status */
u32 clk_m4_spifi_cfg; /* CLK_M4_SPIFI configuration */
u32 clk_m4_spifi_stat; /* CLK_M4_SPIFI status */
u32 clk_m4_gpio_cfg; /* CLK_M4_GPIO configuration */
u32 clk_m4_gpio_stat; /* CLK_M4_GPIO status */
u32 clk_m4_lcd_cfg; /* CLK_M4_LCD configuration */
u32 clk_m4_lcd_stat; /* CLK_M4_LCD status */
u32 clk_m4_ethernet_cfg; /* CLK_M4_ETHERNET configuration */
u32 clk_m4_ethernet_stat; /* CLK_M4_ETHERNET status */
u32 clk_m4_usb0_cfg; /* CLK_M4_USB0 configuration */
u32 clk_m4_usb0_stat; /* CLK_M4_USB0 status */
u32 clk_m4_emc_cfg; /* CLK_M4_EMC configuration */
u32 clk_m4_emc_stat; /* CLK_M4_EMC status */
u32 clk_m4_sdio_cfg; /* CLK_M4_SDIO configuration */
u32 clk_m4_sdio_stat; /* CLK_M4_SDIO status */
u32 clk_m4_dma_cfg; /* CLK_M4_DMA configuration */
u32 clk_m4_dma_stat; /* CLK_M4_DMA status */
u32 clk_m4_m4core_cfg; /* CLK_M4_M4CORE configuration */
u32 clk_m4_m4core_stat; /* CLK_M4_M4CORE status */
u32 rsv4[6];
u32 clk_m4_sct_cfg; /* CLK_M4_SCT configuration */
u32 clk_m4_sct_stat; /* CLK_M4_SCT status */
u32 clk_m4_usb1_cfg; /* CLK_M4_USB1 configuration */
u32 clk_m4_usb1_stat; /* CLK_M4_USB1 status */
u32 clk_m4_emcdiv_cfg; /* CLK_M4_EMCDIV configuration */
u32 clk_m4_emcdiv_stat; /* CLK_M4_EMCDIV status */
u32 rsv5[4];
u32 clk_m4_m0app_cfg; /* CLK_M4_M0_CFG configuration */
u32 clk_m4_m0app_stat; /* CLK_M4_M0_STAT status */
u32 clk_m4_vadc_cfg; /* CLK_M4_VADC_CFG configuration */
u32 clk_m4_vadc_stat; /* CLK_M4_VADC_STAT configuration */
u32 rsv6[24];
u32 clk_m4_wwdt_cfg; /* CLK_M4_WWDT configuration */
u32 clk_m4_wwdt_stat; /* CLK_M4_WWDT status */
u32 clk_m4_usart0_cfg; /* CLK_M4_UART0 configuration */
u32 clk_m4_usart0_stat; /* CLK_M4_UART0 status */
u32 clk_m4_uart1_cfg; /* CLK_M4_UART1 configuration */
u32 clk_m4_uart1_stat; /* CLK_M4_UART1 status */
u32 clk_m4_ssp0_cfg; /* CLK_M4_SSP0 configuration */
u32 clk_m4_ssp0_stat; /* CLK_M4_SSP0 status */
u32 clk_m4_timer0_cfg; /* CLK_M4_TIMER0 configuration */
u32 clk_m4_timer0_stat; /* CLK_M4_TIMER0 status */
u32 clk_m4_timer1_cfg; /* CLK_M4_TIMER1 configuration */
u32 clk_m4_timer1_stat; /* CLK_M4_TIMER1 status */
u32 clk_m4_scu_cfg; /* CLK_M4_SCU configuration */
u32 clk_m4_scu_stat; /* CLK_M4_SCU status */
u32 clk_m4_creg_cfg; /* CLK_M4_CREG configuration */
u32 clk_m4_creg_stat; /* CLK_M4_CREG status */
u32 rsv7[48];
u32 clk_m4_ritimer_cfg; /* CLK_M4_RITIMER configuration */
u32 clk_m4_ritimer_stat; /* CLK_M4_RITIMER status */
u32 clk_m4_usart2_cfg; /* CLK_M4_UART2 configuration */
u32 clk_m4_usart2_stat; /* CLK_M4_UART2 status */
u32 clk_m4_usart3_cfg; /* CLK_M4_UART3 configuration */
u32 clk_m4_usart3_stat; /* CLK_M4_UART3 status */
u32 clk_m4_timer2_cfg; /* CLK_M4_TIMER2 configuration */
u32 clk_m4_timer2_stat; /* CLK_M4_TIMER2 status */
u32 clk_m4_timer3_cfg; /* CLK_M4_TIMER3 configuration */
u32 clk_m4_timer3_stat; /* CLK_M4_TIMER3 status */
u32 clk_m4_ssp1_cfg; /* CLK_M4_SSP1 configuration */
u32 clk_m4_ssp1_stat; /* CLK_M4_SSP1 status */
u32 clk_m4_qei_cfg; /* CLK_M4_QEI configuration */
u32 clk_m4_qei_stat; /* CLK_M4_QEI status */
u32 rsv8[50];
u32 clk_periph_bus_cfg; /* CLK_PERIPH_BUS configuration */
u32 clk_periph_bus_stat; /* CLK_PERIPH_BUS status */
u32 rsv9[2];
u32 clk_periph_core_cfg; /* CLK_PERIPH_CORE configuration */
u32 clk_periph_core_stat; /* CLK_PERIPH_CORE status */
u32 clk_periph_sgpio_cfg; /* CLK_PERIPH_SGPIO configuration */
u32 clk_periph_sgpio_stat; /* CLK_PERIPH_SGPIO status */
u32 rsv10[56];
u32 clk_usb0_cfg; /* CLK_USB0 configuration */
u32 clk_usb0_stat; /* CLK_USB0 status */
u32 rsv11[62];
u32 clk_usb1_cfg; /* CLK_USB1 configuration */
u32 clk_usb1_stat; /* CLK_USB1 status */
u32 rsv12[62];
u32 clk_spi_cfg; /* CLK_SPI configuration */
u32 clk_spi_stat; /* CLK_SPI status */
u32 rsv13[62];
u32 clk_vadc_cfg; /* CLK_VADC configuration */
u32 clk_vadc_stat; /* CLK_VADC status */
};
/*
* CCU1 registers base
*/
#define LPC18XX_CCU1_BASE 0x40051000
#define LPC18XX_CCU1 ((volatile struct lpc18xx_ccu1_regs *) \
LPC18XX_CCU1_BASE)
/*
* All clock configuration registers
*/
#define LPC18XX_CCU1_CLK_RUN_MSK (1 << 0)
/*
* CLK_M4_EMCDIV_CFG register
*/
/* Divider selector */
#define LPC18XX_CCU1_CLK_EMCDIV_CFG_DIV2 (1 << 5)
#endif /* _MACH_CCU_H_ */
/*
* (C) Copyright 2012
*
* Alexander Potashev, Emcraft Systems, aspotashev@emcraft.com
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _MACH_CREG_H_
#define _MACH_CREG_H_
/*
* CREG (Configuration Registers) register map
*/
struct lpc18xx_creg_regs {
u32 rsv0;
u32 creg0; /* Chip configuration register 0 */
u32 rsv1[62];
u32 m4memmap; /* ARM Cortex-M4 memory mapping */
u32 rsv2;
u32 creg1; /* Chip configuration register 1 */
u32 creg2; /* Chip configuration register 2 */
u32 creg3; /* Chip configuration register 3 */
u32 creg4; /* Chip configuration register 4 */
u32 creg5; /* Chip configuration register 5 */
u32 dmamux; /* DMA muxing control */
u32 rsv3[2];
u32 etbcfg; /* ETB RAM configuration */
u32 creg6; /* Chip configuration register 6 */
u32 m4txevent; /* Cortex-M4 TXEV event clear */
u32 rsv4[51];
u32 chipid; /* Part ID */
u32 rsv5[127];
u32 m0txevent; /* Cortex-M0 TXEV event clear */
u32 m0appmemmap; /* ARM Cortex-M0 memory mapping */
};
/*
* CREG registers base
*/
#define LPC18XX_CREG_BASE 0x40043000
#define LPC18XX_CREG ((volatile struct lpc18xx_creg_regs *) \
LPC18XX_CREG_BASE)
/*
* CREG6 register