Commit 77e598e8 authored by Pavel Boldin's avatar Pavel Boldin

RT #90499: STM-SOM-Rev2A U-boot support

parent 13d75651
......@@ -4,6 +4,7 @@
* Yuri Tikhonov, Emcraft Systems, yur@emcraft.com
* Alexander Potashev, Emcraft Systems, aspotashev@emcraft.com
* Vladimir Khusainov, Emcraft Systems, vlad@emcraft.com
* Pavel Boldin, Emcraft Systems, paboldin@emcraft.com
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
......@@ -31,9 +32,14 @@
#include <asm/arch/stm32.h>
#include <asm/arch/stm32f2_gpio.h>
#if CONFIG_SYS_BOARD_REV == 0x2A
# include <asm/arch/fmc.h>
#endif
#include <asm/arch/fsmc.h>
#if (CONFIG_NR_DRAM_BANKS > 0)
#if CONFIG_SYS_BOARD_REV == 0x1A && (CONFIG_NR_DRAM_BANKS > 0)
/*
* Check if RAM configured
*/
......@@ -45,6 +51,166 @@
DECLARE_GLOBAL_DATA_PTR;
static const struct stm32f2_gpio_dsc ext_ram_fsmc_fmc_gpio[] = {
/* Chip is UFBGA176, see DM00077036.pdf for details */
/* N15, FMC_D15 */
{STM32F2_GPIO_PORT_D, STM32F2_GPIO_PIN_10},
/* P14, FMC_D14 */
{STM32F2_GPIO_PORT_D, STM32F2_GPIO_PIN_9},
/* P15, FMC_D13 */
{STM32F2_GPIO_PORT_D, STM32F2_GPIO_PIN_8},
/* R11, FMC_D12 */
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_15},
/* P11, FMC_D11 */
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_14},
/* N11, FMC_D10 */
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_13},
/* R10, FMC_D9 */
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_12},
/* P10, FMC_D8 */
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_11},
/* R9, FMC_D7 */
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_10},
/* P9, FMC_D6 */
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_9},
/* P8, FMC_D5 */
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_8},
/* R8, FMC_D4 */
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_7},
/* C12, FMC_D3 */
{STM32F2_GPIO_PORT_D, STM32F2_GPIO_PIN_1},
/* B12, FMC_D2 */
{STM32F2_GPIO_PORT_D, STM32F2_GPIO_PIN_0},
/* L14, FMC_D1 */
{STM32F2_GPIO_PORT_D, STM32F2_GPIO_PIN_15},
/* M14, FMC_D0 */
{STM32F2_GPIO_PORT_D, STM32F2_GPIO_PIN_14},
/* A3, FMC_NBL1 */
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_1},
/* A4, FMC_NBL0 */
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_0},
/* D10, FMC_NOE */
{STM32F2_GPIO_PORT_D, STM32F2_GPIO_PIN_4},
/* C11, FMC_NWE */
{STM32F2_GPIO_PORT_D, STM32F2_GPIO_PIN_5},
/* B3, FMC_A22 */
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_6},
/* B2, FMC_A21 */
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_5},
/* B1, FMC_A20 */
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_4},
/* A1, FMC_A19 */
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_3},
/* M15, FMC_A18 */
{STM32F2_GPIO_PORT_D, STM32F2_GPIO_PIN_13},
/* N13, FMC_A17 */
{STM32F2_GPIO_PORT_D, STM32F2_GPIO_PIN_12},
/* N14, FMC_A16 */
{STM32F2_GPIO_PORT_D, STM32F2_GPIO_PIN_11},
/* K13, FMC_A15, BA1 */
{STM32F2_GPIO_PORT_G, STM32F2_GPIO_PIN_5},
/* K14, FMC_A14, BA0 */
{STM32F2_GPIO_PORT_G, STM32F2_GPIO_PIN_4},
/* K15, FMC_A13 */
{STM32F2_GPIO_PORT_G, STM32F2_GPIO_PIN_3},
/* L15, FMC_A12 */
{STM32F2_GPIO_PORT_G, STM32F2_GPIO_PIN_2},
/* M7, FMC_A11 */
{STM32F2_GPIO_PORT_G, STM32F2_GPIO_PIN_1},
/* N7, FMC_A10 */
{STM32F2_GPIO_PORT_G, STM32F2_GPIO_PIN_0},
/* P7, FMC_A9 */
{STM32F2_GPIO_PORT_F, STM32F2_GPIO_PIN_15},
/* R7, FMC_A8 */
{STM32F2_GPIO_PORT_F, STM32F2_GPIO_PIN_14},
/* N6, FMC_A7 */
{STM32F2_GPIO_PORT_F, STM32F2_GPIO_PIN_13},
/* P6, FMC_A6 */
{STM32F2_GPIO_PORT_F, STM32F2_GPIO_PIN_12},
/* K3, FMC_A5 */
{STM32F2_GPIO_PORT_F, STM32F2_GPIO_PIN_5},
/* J3, FMC_A4 */
{STM32F2_GPIO_PORT_F, STM32F2_GPIO_PIN_4},
/* J2, FMC_A3 */
{STM32F2_GPIO_PORT_F, STM32F2_GPIO_PIN_3},
/* H2, FMC_A2 */
{STM32F2_GPIO_PORT_F, STM32F2_GPIO_PIN_2},
/* H3, FMC_A1 */
{STM32F2_GPIO_PORT_F, STM32F2_GPIO_PIN_1},
/* E2, FMC_A0 */
{STM32F2_GPIO_PORT_F, STM32F2_GPIO_PIN_0},
#if CONFIG_SYS_BOARD_REV == 0x2A
/* SDRAM only, Revision 0x2A */
/* M4, SDRAM_NE */
{STM32F2_GPIO_PORT_C, STM32F2_GPIO_PIN_2},
/* R6, SDRAM_NRAS */
{STM32F2_GPIO_PORT_F, STM32F2_GPIO_PIN_11},
/* B7, SDRAM_NCAS */
{STM32F2_GPIO_PORT_G, STM32F2_GPIO_PIN_15},
/* J4, SDRAM_NWE */
{STM32F2_GPIO_PORT_H, STM32F2_GPIO_PIN_5},
/* M5, SDRAM_CKE */
{STM32F2_GPIO_PORT_C, STM32F2_GPIO_PIN_3},
/* H14, SDRAM_CLK */
{STM32F2_GPIO_PORT_G, STM32F2_GPIO_PIN_8},
#endif /* CONFIG_SYS_BOARD_REV == 0x2A */
#if CONFIG_SYS_BOARD_REV == 0x1A
/* PSRAM only */
/* B11, FMC_NWAIT */
{STM32F2_GPIO_PORT_D, STM32F2_GPIO_PIN_6},
/* A2, FMC_CRE */
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_2},
/* B5, FMC_NL */
{STM32F2_GPIO_PORT_B, STM32F2_GPIO_PIN_7},
/* D11, FMC_CLK */
{STM32F2_GPIO_PORT_D, STM32F2_GPIO_PIN_3},
#endif /* CONFIG_SYS_BOARD_REV == 0x1A */
#ifdef CONFIG_FSMC_NOR_PSRAM_CS1_ENABLE
{STM32F2_GPIO_PORT_D, STM32F2_GPIO_PIN_7},
#endif
#ifdef CONFIG_FSMC_NOR_PSRAM_CS2_ENABLE
{STM32F2_GPIO_PORT_G, STM32F2_GPIO_PIN_9},
#endif
#ifdef CONFIG_FSMC_NOR_PSRAM_CS3_ENABLE
{STM32F2_GPIO_PORT_G, STM32F2_GPIO_PIN_10},
#endif
#ifdef CONFIG_FSMC_NOR_PSRAM_CS4_ENABLE
{STM32F2_GPIO_PORT_G, STM32F2_GPIO_PIN_12},
#endif
};
/*
* Init FMC/FSMC GPIOs based
*/
static int fmc_fsmc_setup_gpio(void)
{
int rv = 0;
int i;
/*
* Connect GPIOs to FMC controller
*/
for (i = 0; i < ARRAY_SIZE(ext_ram_fsmc_fmc_gpio); i++) {
rv = stm32f2_gpio_config(&ext_ram_fsmc_fmc_gpio[i],
STM32F2_GPIO_ROLE_FMC);
if (rv)
goto out;
}
fsmc_gpio_init_done = 1;
out:
return rv;
}
/*
* Early hardware init.
*/
......@@ -52,6 +218,10 @@ int board_init(void)
{
int rv;
rv = fmc_fsmc_setup_gpio();
if (rv)
return rv;
#if !defined(CONFIG_SYS_NO_FLASH)
if ((rv = fsmc_nor_psram_init(CONFIG_SYS_FLASH_CS, CONFIG_SYS_FSMC_FLASH_BCR,
CONFIG_SYS_FSMC_FLASH_BTR,
......@@ -73,6 +243,7 @@ int checkboard(void)
return 0;
}
#if CONFIG_SYS_BOARD_REV == 0x1A
/*
* Setup external RAM.
*/
......@@ -157,6 +328,138 @@ int dram_init(void)
out:
return rv;
}
#endif /* CONFIG_SYS_BOARD_REV == 0x1A */
#if CONFIG_SYS_BOARD_REV == 0x2A
/*
* STM32 RCC FMC specific definitions
*/
#define STM32_RCC_ENR_FMC (1 << 0) /* FMC module clock */
static inline u32 _ns2clk(u32 ns, u32 freq)
{
uint32_t tmp = freq/1000000;
return (tmp * ns) / 1000;
}
#define NS2CLK(ns) (_ns2clk(ns, freq))
/*
* Following are timings for M12L2561616A-6BI, from corresponding datasheet
*/
#define SDRAM_CAS 3
#define SDRAM_NB 1 /* Number of banks */
#define SDRAM_MWID 1 /* 16 bit memory */
#define SDRAM_NR 0x2 /* 13-bit row */
#define SDRAM_NC 0x1 /* 9-bit col */
#define SDRAM_TRRD NS2CLK(12)
#define SDRAM_TRCD NS2CLK(18)
#define SDRAM_TRP NS2CLK(18)
#define SDRAM_TRAS NS2CLK(42)
#define SDRAM_TRC NS2CLK(60)
#define SDRAM_TRFC NS2CLK(60)
#define SDRAM_TCDL (1 - 1)
#define SDRAM_TRDL NS2CLK(12)
#define SDRAM_TBDL (1 - 1)
#define SDRAM_TREF (NS2CLK(64000000 / 8192) - 20)
#define SDRAM_TCCD (1 - 1)
#define SDRAM_TXSR SDRAM_TRFC /* Row cycle time after precharge */
#define SDRAM_TMRD (3 - 1) /* Page 10, Mode Register Set */
/* Last data in to row precharge, need also comply ineq on page 1648 */
#define SDRAM_TWR max(\
(int)max((int)SDRAM_TRDL, (int)(SDRAM_TRAS - SDRAM_TRCD)), \
(int)(SDRAM_TRC - SDRAM_TRCD - SDRAM_TRP)\
)
int dram_init(void)
{
u32 freq;
int rv;
/*
* Enable FMC interface clock
*/
STM32_RCC->ahb3enr |= STM32_RCC_ENR_FMC;
/*
* Get frequency for NS2CLK calculation.
*/
freq = clock_get(CLOCK_HCLK) / CONFIG_SYS_RAM_FREQ_DIV;
STM32_SDRAM_FMC->sdcr1 = (
CONFIG_SYS_RAM_FREQ_DIV << FMC_SDCR_SDCLK_SHIFT |
SDRAM_CAS << FMC_SDCR_CAS_SHIFT |
SDRAM_NB << FMC_SDCR_NB_SHIFT |
SDRAM_MWID << FMC_SDCR_MWID_SHIFT |
SDRAM_NR << FMC_SDCR_NR_SHIFT |
SDRAM_NC << FMC_SDCR_NC_SHIFT |
1 << FMC_SDCR_RPIPE_SHIFT |
1 << FMC_SDCR_RBURST_SHIFT
);
STM32_SDRAM_FMC->sdtr1 = (
SDRAM_TRCD << FMC_SDTR_TRCD_SHIFT |
SDRAM_TRP << FMC_SDTR_TRP_SHIFT |
SDRAM_TWR << FMC_SDTR_TWR_SHIFT |
SDRAM_TRC << FMC_SDTR_TRC_SHIFT |
SDRAM_TRAS << FMC_SDTR_TRAS_SHIFT |
SDRAM_TXSR << FMC_SDTR_TXSR_SHIFT |
SDRAM_TMRD << FMC_SDTR_TMRD_SHIFT
);
STM32_SDRAM_FMC->sdcmr = FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_START_CLOCK;
udelay(200); /* 200 us delay, page 10, "Power-Up" */
STM32_SDRAM_FMC->sdcmr = FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_PRECHARGE;
udelay(100);
STM32_SDRAM_FMC->sdcmr = (
FMC_SDCMR_BANK_1 | FMC_SDCMR_MODE_AUTOREFRESH |
7 << FMC_SDCMR_NRFS_SHIFT
);
udelay(100);
#define SDRAM_MODE_BL_SHIFT 0
#define SDRAM_MODE_CAS_SHIFT 4
#define SDRAM_MODE_BL 0
#define SDRAM_MODE_CAS SDRAM_CAS
STM32_SDRAM_FMC->sdcmr = FMC_SDCMR_BANK_1 |
(
SDRAM_MODE_BL << SDRAM_MODE_BL_SHIFT |
SDRAM_MODE_CAS << SDRAM_MODE_CAS_SHIFT
) << FMC_SDCMR_MODE_REGISTER_SHIFT | FMC_SDCMR_MODE_WRITE_MODE;
udelay(100);
STM32_SDRAM_FMC->sdcmr = FMC_SDCMR_BANK_1;
/* Refresh timer */
STM32_SDRAM_FMC->sdrtr = SDRAM_TREF;
/*
* Fill in global info with description of SRAM configuration
*/
gd->bd->bi_dram[0].start = CONFIG_SYS_RAM_BASE;
gd->bd->bi_dram[0].size = CONFIG_SYS_RAM_SIZE;
rv = 0;
cortex_m3_mpu_full_access();
return rv;
}
#endif /* CONFIG_SYS_BOARD_REV == 0x2A */
#ifdef CONFIG_STM32_ETH
/*
......
......@@ -284,15 +284,12 @@ static void clock_setup(void)
* STM lib code as well.
*/
STM32_RCC->cr |= STM32_RCC_CR_PLLON;
while (STM32_RCC->cr & STM32_RCC_CR_PLLRDY);
while (!(STM32_RCC->cr & STM32_RCC_CR_PLLRDY));
/*
* Select PLL as system source if it's setup OK, and HSE otherwise
*/
if (!(STM32_RCC->cr & STM32_RCC_CR_PLLRDY))
val = STM32_RCC_CFGR_SWS_PLL;
else
val = STM32_RCC_CFGR_SWS_HSE;
val = STM32_RCC_CFGR_SWS_PLL;
# else
/*
* Select HSE as system source
......
......@@ -119,17 +119,18 @@ static const struct stm32f2_gpio_dsc ext_ram_fsmc_gpio[] = {
#endif
};
int fsmc_gpio_init_done = 0;
int fsmc_nor_psram_init(u32 cs, u32 bcr, u32 btr, u32 bwtr)
{
int rv = 0;
static int common_init_done = 0;
cs--;
if (cs > 3)
return -EINVAL;
if (!common_init_done) {
if (!fsmc_gpio_init_done) {
int i;
/*
......@@ -142,14 +143,14 @@ int fsmc_nor_psram_init(u32 cs, u32 bcr, u32 btr, u32 bwtr)
goto out;
}
/*
* Enable FSMC interface clock
*/
STM32_RCC->ahb3enr |= STM32_RCC_ENR_FSMC;
common_init_done = 1;
fsmc_gpio_init_done = 1;
}
/*
* Enable FSMC interface clock
*/
STM32_RCC->ahb3enr |= STM32_RCC_ENR_FSMC;
/*
* Fake BCR read; if don't do this, then BCR remains configured
* with defaults.
......
/*
* (C) Copyright 2013
*
* Pavel Boldin, Emcraft Systems, paboldin@emcraft.com
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef _MACH_FMC_H_
#define _MACH_FMC_H_
struct stm32_fmc_regs {
/* Control registers */
u32 sdcr1;
u32 sdcr2;
/* Timing registers */
u32 sdtr1;
u32 sdtr2;
/* Mode register */
u32 sdcmr;
/* Refresh timing register */
u32 sdrtr;
/* Status register */
u32 sdsr;
};
/*
* FMC registers base
*/
#define STM32_SDRAM_FMC_BASE 0xA0000140
#define STM32_SDRAM_FMC ((volatile struct stm32_fmc_regs *) \
STM32_SDRAM_FMC_BASE)
/* Control register SDCR */
#define FMC_SDCR_RPIPE_SHIFT 13 /* RPIPE bit shift */
#define FMC_SDCR_RBURST_SHIFT 12 /* RBURST bit shift */
#define FMC_SDCR_SDCLK_SHIFT 10 /* SDRAM clock divisor shift */
#define FMC_SDCR_WP_SHIFT 9 /* Write protection shift */
#define FMC_SDCR_CAS_SHIFT 7 /* CAS latency shift */
#define FMC_SDCR_NB_SHIFT 6 /* Number of banks shift */
#define FMC_SDCR_MWID_SHIFT 4 /* Memory width shift */
#define FMC_SDCR_NR_SHIFT 2 /* Number of row address bits shift */
#define FMC_SDCR_NC_SHIFT 0 /* Number of col address bits shift */
/* Timings register SDTR */
#define FMC_SDTR_TMRD_SHIFT 0 /* Load mode register to active */
#define FMC_SDTR_TXSR_SHIFT 4 /* Exit self-refresh time */
#define FMC_SDTR_TRAS_SHIFT 8 /* Self-refresh time */
#define FMC_SDTR_TRC_SHIFT 12 /* Row cycle delay */
#define FMC_SDTR_TWR_SHIFT 16 /* Recovery delay */
#define FMC_SDTR_TRP_SHIFT 20 /* Row precharge delay */
#define FMC_SDTR_TRCD_SHIFT 24 /* Row-to-column delay */
#define FMC_SDCMR_NRFS_SHIFT 5
#define FMC_SDCMR_MODE_START_CLOCK 1
#define FMC_SDCMR_MODE_PRECHARGE 2
#define FMC_SDCMR_MODE_AUTOREFRESH 3
#define FMC_SDCMR_MODE_WRITE_MODE 4
#define FMC_SDCMR_BANK_1 (1 << 4)
#define FMC_SDCMR_BANK_2 (1 << 3)
#define FMC_SDCMR_MODE_REGISTER_SHIFT 9
#endif /* _MACH_FMC_H_ */
......@@ -68,4 +68,6 @@
*/
int fsmc_nor_psram_init(u32 num, u32 bcr, u32 btr, u32 bwtr);
extern int fsmc_gpio_init_done;
#endif /* _MACH_FSMC_H_ */
......@@ -72,6 +72,7 @@ enum stm32f2_gpio_role {
STM32F2_GPIO_ROLE_ETHERNET, /* MAC */
STM32F2_GPIO_ROLE_MCO, /* MC external output clock */
STM32F2_GPIO_ROLE_FSMC, /* FSMC static memory controller */
STM32F2_GPIO_ROLE_FMC = STM32F2_GPIO_ROLE_FSMC,
STM32F2_GPIO_ROLE_GPOUT, /* GPOUT */
STM32F2_GPIO_ROLE_LAST /* for internal usage, must be last */
......
......@@ -4,6 +4,7 @@
* Yuri Tikhonov, Emcraft Systems, yur@emcraft.com
* Alexander Potashev, Emcraft Systems, aspotashev@emcraft.com
* Vladimir Khusainov, Emcraft Systems, vlad@emcraft.com
* Pavel Boldin, Emcraft Systems, paboldin@emcraft.com
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
......@@ -22,12 +23,15 @@
*/
/*
* Configuration settings for the STMicroelectronic STM3220G-EVAL board.
* Configuration settings for the Emcraft's STM SOM Rev 1.A and 2.A
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#define CONFIG_SYS_BOARD_REV 0x2A
/*
* Disable debug messages
*/
......@@ -57,12 +61,20 @@
#define CONFIG_DISPLAY_CPUINFO 1
#define CONFIG_DISPLAY_BOARDINFO 1
#define CONFIG_SYS_BOARD_REV_STR "Rev 1.A"
#if CONFIG_SYS_BOARD_REV == 0x2A
# define CONFIG_SYS_BOARD_REV_STR "Rev 2.A"
#elif CONFIG_SYS_BOARD_REV == 0x1A
# define CONFIG_SYS_BOARD_REV_STR "Rev 1.A"
#endif
/*
* Monitor prompt
*/
#define CONFIG_SYS_PROMPT "STM-SOM> "
#if CONFIG_SYS_BOARD_REV == 0x2A
# define CONFIG_SYS_PROMPT "STM32F4X9-SOM> "
#elif CONFIG_SYS_BOARD_REV == 0x1A
# define CONFIG_SYS_PROMPT "STM-SOM> "
#endif
/*
* We want to call the CPU specific initialization
......@@ -118,30 +130,45 @@
#define FSMC_NOR_PSRAM_CS_ADDR(n) \
(0x60000000 + ((n) - 1) * 0x4000000)
#if CONFIG_SYS_BOARD_REV == 0x2A
/*
* Configuration of the external PSRAM memory
* Configuration of the external SDRAM memory for Rev 2.A
*/
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_RAM_SIZE (16 * 1024 * 1024)
#define CONFIG_SYS_RAM_CS 1
# define CONFIG_NR_DRAM_BANKS 1
# define CONFIG_SYS_RAM_SIZE (32 * 1024 * 1024)
# define CONFIG_SYS_RAM_CS 1
# define CONFIG_SYS_RAM_FREQ_DIV 2
# define CONFIG_SYS_RAM_BASE 0xC0000000
#define CONFIG_SYS_RAM_BURST
#define CONFIG_SYS_FSMC_PSRAM_BCR 0x00005059
#define CONFIG_SYS_FSMC_PSRAM_BTR 0x10000904
#define CONFIG_SYS_FSMC_PSRAM_BWTR 0x10000804
#define CONFIG_FSMC_NOR_PSRAM_CS2_ENABLE
#elif CONFIG_SYS_BOARD_REV == 0x1A
/*
* Configuration of the external PSRAM memory for Rev 1.A
*/
# define CONFIG_NR_DRAM_BANKS 1
# define CONFIG_SYS_RAM_SIZE (16 * 1024 * 1024)
# define CONFIG_SYS_RAM_CS 1
# define CONFIG_SYS_RAM_BURST
# define CONFIG_SYS_FSMC_PSRAM_BCR 0x00005059
# define CONFIG_SYS_FSMC_PSRAM_BTR 0x10000904
# define CONFIG_SYS_FSMC_PSRAM_BWTR 0x10000804
# define CONFIG_FSMC_NOR_PSRAM_CS1_ENABLE
# define CONFIG_SYS_RAM_BASE FSMC_NOR_PSRAM_CS_ADDR(CONFIG_SYS_RAM_CS)
#define CONFIG_SYS_RAM_BASE FSMC_NOR_PSRAM_CS_ADDR(CONFIG_SYS_RAM_CS)
#endif /* CONFIG_SYS_BOARD_REV is 1A */
/*
* Configuration of the external Flash memory
* Configuration of the external Flash memory, common for both revisions
*/
#define CONFIG_SYS_FLASH_CS 2
#define CONFIG_SYS_FSMC_FLASH_BCR 0x00005015
#define CONFIG_SYS_FSMC_FLASH_BCR 0x00105055
#define CONFIG_SYS_FSMC_FLASH_BTR 0x00021206
#define CONFIG_SYS_FSMC_FLASH_BWTR 0x00021106
#define CONFIG_FSMC_NOR_PSRAM_CS1_ENABLE
#define CONFIG_FSMC_NOR_PSRAM_CS2_ENABLE
#define CONFIG_SYS_FLASH_BANK1_BASE FSMC_NOR_PSRAM_CS_ADDR(CONFIG_SYS_FLASH_CS)
......@@ -168,11 +195,30 @@
* Serial console configuration
*/
#define CONFIG_STM32_USART_CONSOLE
#define CONFIG_STM32_USART_PORT 3 /* USART3 */
#define CONFIG_STM32_USART_TX_IO_PORT 2 /* PORTC */
#define CONFIG_STM32_USART_RX_IO_PORT 2 /* PORTC */
#define CONFIG_STM32_USART_TX_IO_PIN 10 /* GPIO10 */
#define CONFIG_STM32_USART_RX_IO_PIN 11 /* GPIO11 */
#if CONFIG_SYS_BOARD_REV == 0x2A
/* Rev 2A console: USART1, TX PB.6, RX PA.10 */
# define CONFIG_STM32_USART_PORT 1 /* USART1 */
# define CONFIG_STM32_USART_TX_IO_PORT 1 /* PORTB */
# define CONFIG_STM32_USART_TX_IO_PIN 6 /* GPIO6 */
# define CONFIG_STM32_USART_RX_IO_PORT 0 /* PORTA */
# define CONFIG_STM32_USART_RX_IO_PIN 10 /* GPIO10 */
#elif CONFIG_SYS_BOARD_REV == 0x1A
/* Rev 1A console: USART3, TX PC.10, RX PC.11 */
# define CONFIG_STM32_USART_PORT 3 /* USART3 */
# define CONFIG_STM32_USART_TX_IO_PORT 2 /* PORTC */
# define CONFIG_STM32_USART_TX_IO_PIN 10 /* GPIO10 */
# define CONFIG_STM32_USART_RX_IO_PORT 2 /* PORTC */
# define CONFIG_STM32_USART_RX_IO_PIN 11 /* GPIO11 */
#endif
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
......@@ -259,18 +305,33 @@
*/
#define CONFIG_BOOTDELAY 3
#define CONFIG_ZERO_BOOTDELAY_CHECK
#define CONFIG_HOSTNAME stm-som
#define CONFIG_BOOTARGS "stm32_platform=stm-som "\
"console=ttyS2,115200 panic=10"
#define CONFIG_BOOTCOMMAND "run flashboot"
#if CONFIG_SYS_BOARD_REV == 0x2A
/* Rev 2.A boot args and env */
# define CONFIG_HOSTNAME stm32f4x9-som
# define CONFIG_BOOTARGS "stm32_platform=stm32f4x9-som "\
"console=ttyS0,115200 panic=10"
# define LOADADDR "0xC0000000"
#elif CONFIG_SYS_BOARD_REV == 0x1A
/* Rev 1.A boot args and env */
# define CONFIG_HOSTNAME stm-som
# define CONFIG_BOOTARGS "stm32_platform=stm-som "\
"console=ttyS2,115200 panic=10"
# define LOADADDR "0x60000000"
#endif
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
/*
* Short-cuts to some useful commands (macros)
*/
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=0x60000000\0" \
"loadaddr=" LOADADDR "\0" \
"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:eth0:off\0" \
"flashaddr=64020000\0" \
"flashboot=run addip;bootm ${flashaddr}\0" \
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment