Commit 8148f3d8 authored by Sergei Miroshnichenko's avatar Sergei Miroshnichenko

RM#1045 Add configuration for STmicro STM32F769I Discovery board

parent b76a4623
......@@ -3263,6 +3263,9 @@ stm32f746-discovery_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm_cortexm3 stm32f746-discovery \
stm stm32
stm32f769i-discovery_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm_cortexm3 stm32f7-som emcraft stm32
stm3220g-eval_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm_cortexm3 stm3220g-eval stm stm32
......
......@@ -42,6 +42,129 @@
DECLARE_GLOBAL_DATA_PTR;
static const struct stm32f2_gpio_dsc ext_ram_fsmc_fmc_gpio[] = {
#if defined(CONFIG_SYS_STM32F769I_DISCO)
/* +L12, FMC_D0 */
{STM32F2_GPIO_PORT_D, STM32F2_GPIO_PIN_14},
/* +K13, FMC_D1 */
{STM32F2_GPIO_PORT_D, STM32F2_GPIO_PIN_15},
/* +B12, FMC_D2 */
{STM32F2_GPIO_PORT_D, STM32F2_GPIO_PIN_0},
/* +C12, FMC_D3 */
{STM32F2_GPIO_PORT_D, STM32F2_GPIO_PIN_1},
/* +R8, FMC_D4 */
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_7},
/* +N9, FMC_D5 */
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_8},
/* +P9, FMC_D6 */
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_9},
/* +R9, FMC_D7 */
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_10},
/* +P10, FMC_D8 */
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_11},
/* +R10, FMC_D9 */
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_12},
/* +R12, FMC_D10 */
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_13},
/* +P11, FMC_D11 */
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_14},
/* +R11, FMC_D12 */
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_15},
/* +L15, FMC_D13 */
{STM32F2_GPIO_PORT_D, STM32F2_GPIO_PIN_8},
/* +L14, FMC_D14 */
{STM32F2_GPIO_PORT_D, STM32F2_GPIO_PIN_9},
/* +K15, FMC_D15 */
{STM32F2_GPIO_PORT_D, STM32F2_GPIO_PIN_10},
/* +P14, FMC_D16 */
{STM32F2_GPIO_PORT_H, STM32F2_GPIO_PIN_8},
/* +N14, FMC_D17 */
{STM32F2_GPIO_PORT_H, STM32F2_GPIO_PIN_9},
/* +P15, FMC_D18 */
{STM32F2_GPIO_PORT_H, STM32F2_GPIO_PIN_10},
/* +N15, FMC_D19 */
{STM32F2_GPIO_PORT_H, STM32F2_GPIO_PIN_11},
/* +M15, FMC_D20 */
{STM32F2_GPIO_PORT_H, STM32F2_GPIO_PIN_12},
/* +E12, FMC_D21 */
{STM32F2_GPIO_PORT_H, STM32F2_GPIO_PIN_13},
/* +E13, FMC_D22 */
{STM32F2_GPIO_PORT_H, STM32F2_GPIO_PIN_14},
/* +D13, FMC_D23 */
{STM32F2_GPIO_PORT_H, STM32F2_GPIO_PIN_15},
/* +E14, FMC_D24 */
{STM32F2_GPIO_PORT_I, STM32F2_GPIO_PIN_0},
/* +D14, FMC_D25 */
{STM32F2_GPIO_PORT_I, STM32F2_GPIO_PIN_1},
/* +C14, FMC_D26 */
{STM32F2_GPIO_PORT_I, STM32F2_GPIO_PIN_2},
/* +C13, FMC_D27 */
{STM32F2_GPIO_PORT_I, STM32F2_GPIO_PIN_3},
/* +D6, FMC_D28 */
{STM32F2_GPIO_PORT_I, STM32F2_GPIO_PIN_6},
/* +D4, FMC_D29 */
{STM32F2_GPIO_PORT_I, STM32F2_GPIO_PIN_7},
/* +E4, FMC_D30 */
{STM32F2_GPIO_PORT_I, STM32F2_GPIO_PIN_9},
/* +D5, FMC_D31 */
{STM32F2_GPIO_PORT_I, STM32F2_GPIO_PIN_10},
/* +D2, FMC_A0 */
{STM32F2_GPIO_PORT_F, STM32F2_GPIO_PIN_0},
/* +E2, FMC_A1 */
{STM32F2_GPIO_PORT_F, STM32F2_GPIO_PIN_1},
/* +G2, FMC_A2 */
{STM32F2_GPIO_PORT_F, STM32F2_GPIO_PIN_2},
/* +H2, FMC_A3 */
{STM32F2_GPIO_PORT_F, STM32F2_GPIO_PIN_3},
/* +J2, FMC_A4 */
{STM32F2_GPIO_PORT_F, STM32F2_GPIO_PIN_4},
/* +K3, FMC_A5 */
{STM32F2_GPIO_PORT_F, STM32F2_GPIO_PIN_5},
/* +M6, FMC_A6 */
{STM32F2_GPIO_PORT_F, STM32F2_GPIO_PIN_12},
/* +N6, FMC_A7 */
{STM32F2_GPIO_PORT_F, STM32F2_GPIO_PIN_13},
/* +P6, FMC_A8 */
{STM32F2_GPIO_PORT_F, STM32F2_GPIO_PIN_14},
/* +M8, FMC_A9 */
{STM32F2_GPIO_PORT_F, STM32F2_GPIO_PIN_15},
/* +N7, FMC_A10 */
{STM32F2_GPIO_PORT_G, STM32F2_GPIO_PIN_0},
/* +M7, FMC_A11 */
{STM32F2_GPIO_PORT_G, STM32F2_GPIO_PIN_1},
/* +M13, FMC_A12 */
{STM32F2_GPIO_PORT_G, STM32F2_GPIO_PIN_2},
/* +A6, FMC_NBL0 */
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_0},
/* +A5, FMC_NBL1 */
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_1},
/* +C3, FMC_NBL2 */
{STM32F2_GPIO_PORT_I, STM32F2_GPIO_PIN_4},
/* +D3, FMC_NBL3 */
{STM32F2_GPIO_PORT_I, STM32F2_GPIO_PIN_5},
/* +N12, FMC_BA0 */
{STM32F2_GPIO_PORT_G, STM32F2_GPIO_PIN_4},
/* +N11, FMC_BA1 */
{STM32F2_GPIO_PORT_G, STM32F2_GPIO_PIN_5},
/* SDRAM */
/* +J4, FMC_SDNE0 */
{STM32F2_GPIO_PORT_H, STM32F2_GPIO_PIN_3},
/* +K4, FMC_SDCKE0 */
{STM32F2_GPIO_PORT_H, STM32F2_GPIO_PIN_2},
/* +P8, FMC_SDNRAS */
{STM32F2_GPIO_PORT_F, STM32F2_GPIO_PIN_11},
/* +B7, FMC_SDNCAS */
{STM32F2_GPIO_PORT_G, STM32F2_GPIO_PIN_15},
/* +J3, FMC_SDNWE */
{STM32F2_GPIO_PORT_H, STM32F2_GPIO_PIN_5},
/* +H14, FMC_SDCLK */
{STM32F2_GPIO_PORT_G, STM32F2_GPIO_PIN_8},
#else /* CONFIG_SYS_STM32F769I_DISCO */
/* K15, FMC_D15 */
{STM32F2_GPIO_PORT_D, STM32F2_GPIO_PIN_10},
/* L14, FMC_D14 */
......@@ -161,6 +284,7 @@ static const struct stm32f2_gpio_dsc ext_ram_fsmc_fmc_gpio[] = {
#ifdef CONFIG_FSMC_NOR_PSRAM_CS4_ENABLE
{STM32F2_GPIO_PORT_G, STM32F2_GPIO_PIN_12},
#endif
#endif /* CONFIG_SYS_STM32F769I_DISCO */
};
#ifdef CONFIG_VIDEO_STM32F4_LTDC
......@@ -348,8 +472,13 @@ Done:
*/
int checkboard(void)
{
#if defined(CONFIG_SYS_STM32F769I_DISCO)
printf("Board: STM32F769I-DISCO %s, www.emcraft.com\n",
CONFIG_SYS_BOARD_REV_STR);
#else
printf("Board: STM32F7 SOM Rev %s, www.emcraft.com\n",
CONFIG_SYS_BOARD_REV_STR);
#endif /* CONFIG_SYS_STM32F769I_DISCO */
return 0;
}
......@@ -369,6 +498,35 @@ static inline u32 _ns2clk(u32 ns, u32 freq)
#define NS2CLK(ns) (_ns2clk(ns, freq))
#if defined(CONFIG_SYS_STM32F769I_DISCO)
/*
* Following are timings for MT48LC4M32B2, from corresponding datasheet
*/
#define SDRAM_CAS 3
#define SDRAM_NB 4 /* Number of banks */
#define SDRAM_MWID 2 /* 32 bit memory */
#define SDRAM_NR 0x1 /* 12-bit row */
#define SDRAM_NC 0x0 /* 8-bit col */
#define SDRAM_TRRD NS2CLK(12)
#define SDRAM_TRCD NS2CLK(18)
#define SDRAM_TRP NS2CLK(18)
#define SDRAM_TRAS NS2CLK(42)
#define SDRAM_TRC NS2CLK(60)
#define SDRAM_TRFC NS2CLK(60)
#define SDRAM_TCDL (1 - 1)
#define SDRAM_TRDL NS2CLK(12)
#define SDRAM_TBDL (1 - 1)
#define SDRAM_TREF (NS2CLK(64000000 / 8192) - 20)
#define SDRAM_TCCD (1 - 1)
#define SDRAM_TXSR NS2CLK(70)
#define SDRAM_TMRD (3 - 1)
#else /* CONFIG_SYS_STM32F769I_DISCO */
/*
* Following are timings for M12L2561616A-6BI, from corresponding datasheet
*/
......@@ -394,6 +552,8 @@ static inline u32 _ns2clk(u32 ns, u32 freq)
#define SDRAM_TXSR SDRAM_TRFC /* Row cycle time after precharge */
#define SDRAM_TMRD (3 - 1) /* Page 10, Mode Register Set */
#endif /* CONFIG_SYS_STM32F769I_DISCO */
/* Last data in to row precharge, need also comply ineq on page 1648 */
#define SDRAM_TWR max(\
(int)max((int)SDRAM_TRDL, (int)(SDRAM_TRAS - SDRAM_TRCD)), \
......@@ -531,6 +691,7 @@ void start_ram(void)
udelay(60);
}
#if !defined(CONFIG_SYS_NO_FLASH)
#define NOP10() do { nop(); nop(); nop(); nop(); nop(); \
nop(); nop(); nop(); nop(); nop(); \
} while(0);
......@@ -609,6 +770,7 @@ u32 flash_check_flag(void *src, void *dst, int cnt, int portwidth)
out:
return flag;
}
#endif /* !CONFIG_SYS_NO_FLASH */
#ifdef CONFIG_STM32_ETH
/*
......
......@@ -100,7 +100,15 @@
# if (CONFIG_STM32_PLL_Q < 4) || (CONFIG_STM32_PLL_Q > 15)
# error "Incorrect PLL_Q value."
# endif
#endif
# if defined(CONFIG_SYS_STM32F769I_DISCO)
# if !defined(CONFIG_STM32_PLL_R)
# error "PLL_R must be set for STM32F769."
# endif
# if (CONFIG_STM32_PLL_R < 2) || (CONFIG_STM32_PLL_R > 7)
# error "Incorrect PLL_R value."
# endif
# endif /* CONFIG_SYS_STM32F769I_DISCO */
#endif /* CONFIG_STM32_SYS_CLK_PLL */
/*
* Internal oscillator value
......@@ -211,6 +219,9 @@
#define STM32_RCC_PLLCFGR_PLLQ_BIT 24 /* Div factor for USB,SDIO,.. */
#define STM32_RCC_PLLCFGR_PLLQ_MSK 0xF
#define STM32_RCC_PLLCFGR_PLLR_BIT 28 /* Div factor for DSI clock. */
#define STM32_RCC_PLLCFGR_PLLR_MSK 0x7
#define STM32_RCC_DCKCFGR_PLLSAIDIVR (3 << 16)
#define STM32_RCC_PLLSAIDivR_Div8 (2 << 16)
......@@ -380,6 +391,9 @@ static void clock_setup(void)
val |= CONFIG_STM32_PLL_N << STM32_RCC_PLLCFGR_PLLN_BIT;
val |= ((CONFIG_STM32_PLL_P >> 1) - 1) << STM32_RCC_PLLCFGR_PLLP_BIT;
val |= CONFIG_STM32_PLL_Q << STM32_RCC_PLLCFGR_PLLQ_BIT;
#if defined(CONFIG_STM32_PLL_R)
val |= CONFIG_STM32_PLL_R << STM32_RCC_PLLCFGR_PLLR_BIT;
#endif
STM32_RCC->pllcfgr = val;
......
......@@ -308,25 +308,25 @@ struct stm_eth_dev {
/*
* Ethernet GPIOs:
* STM32F7-SOM STM32F7-DISCO
* ETH_MII_RX_CLK/ETH_RMII_REF_CLK---> PA1 =
* ETH_MDIO -------------------------> PA2 =
* ETH_MII_RX_DV/ETH_RMII_CRS_DV ----> PA7 =
* ETH_PPS_OUT ----------------------> PB5 -
* ETH_MII_TXD3 ---------------------> PB8 -
* ETH_MDC --------------------------> PC1 =
* ETH_MII_TXD2 ---------------------> PC2 -
* ETH_MII_TX_CLK -------------------> PC3 -
* ETH_MII_RXD0/ETH_RMII_RXD0 -------> PC4 =
* ETH_MII_RXD1/ETH_RMII_RXD1 -------> PC5 =
* ETH_MII_TX_EN/ETH_RMII_TX_EN -----> PG11 =
* ETH_MII_TXD0/ETH_RMII_TXD0 -------> PG13 =
* ETH_MII_TXD1/ETH_RMII_TXD1 -------> PG14 =
* ETH_MII_CRS ----------------------> PH2 -
* ETH_MII_COL ----------------------> PH3 -
* ETH_MII_RXD2 ---------------------> PH6 -
* ETH_MII_RXD3 ---------------------> PH7 -
* ETH_MII_RX_ER --------------------> PI10 PG2
* STM32F7-SOM STM32F746-DISCO STM32F769I-DISCO
* ETH_MII_RX_CLK/ETH_RMII_REF_CLK---> PA1 = =
* ETH_MDIO -------------------------> PA2 = =
* ETH_MII_RX_DV/ETH_RMII_CRS_DV ----> PA7 = =
* ETH_PPS_OUT ----------------------> PB5 - -
* ETH_MII_TXD3 ---------------------> PB8 - -
* ETH_MDC --------------------------> PC1 = =
* ETH_MII_TXD2 ---------------------> PC2 - -
* ETH_MII_TX_CLK -------------------> PC3 - -
* ETH_MII_RXD0/ETH_RMII_RXD0 -------> PC4 = =
* ETH_MII_RXD1/ETH_RMII_RXD1 -------> PC5 = =
* ETH_MII_TX_EN/ETH_RMII_TX_EN -----> PG11 = =
* ETH_MII_TXD0/ETH_RMII_TXD0 -------> PG13 = =
* ETH_MII_TXD1/ETH_RMII_TXD1 -------> PG14 = =
* ETH_MII_CRS ----------------------> PH2 - -
* ETH_MII_COL ----------------------> PH3 - -
* ETH_MII_RXD2 ---------------------> PH6 - -
* ETH_MII_RXD3 ---------------------> PH7 - -
* ETH_MII_RX_ER --------------------> PI10 PG2 PD5
*/
static struct stm32f2_gpio_dsc mac_gpio[] = {
{STM32F2_GPIO_PORT_A, 1},
......@@ -359,6 +359,8 @@ static struct stm32f2_gpio_dsc mac_gpio[] = {
/* ETH_MII_RX_ER is different on STM32F7-{SOM,DISCO} */
#ifndef CONFIG_SYS_STM32F7_DISCO
{STM32F2_GPIO_PORT_I, 10}
#elif defined(CONFIG_SYS_STM32F769I_DISCO)
{STM32F2_GPIO_PORT_D, 5}
#else
{STM32F2_GPIO_PORT_G, 2}
#endif
......
/*
* (C) Copyright 2011-2016
*
* Yuri Tikhonov, Emcraft Systems, yur@emcraft.com
* Sergei Miroshnichenko, Emcraft Systems, sergeimir@emcraft.com
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Configuration settings for the STmicro STM32F769I Discovery board
*/
#ifndef __CONFIG_H
#define __CONFIG_H
#undef DEBUG
/*
* This is an ARM Cortex-M7 CPU core.
* Also use the common Cortex-M3 and Cortex-M4 code.
*/
#define CONFIG_SYS_ARMCORTEXM3
#define CONFIG_SYS_ARMCORTEXM4
#define CONFIG_SYS_ARMCORTEXM7
/*
* This is an STM32 and STM32F7 device.
*/
#define CONFIG_SYS_STM32
#define CONFIG_SYS_STM32F7
#undef CONFIG_SYS_STM32F7_DISCO
#define CONFIG_SYS_STM32F769I_DISCO
/*
* Enable GPIO driver
*/
#define CONFIG_STM32F2_GPIO
/*
* Display CPU and Board information
*/
#define CONFIG_DISPLAY_CPUINFO 1
#define CONFIG_DISPLAY_BOARDINFO 1
#define CONFIG_SYS_BOARD_REV_STR "Revision B-01"
/*
* Monitor prompt
*/
#define CONFIG_SYS_PROMPT "STM32F769I-DISCO> "
/*
* We want to call the CPU specific initialization
*/
#define CONFIG_ARCH_CPU_INIT
/*
* Clock configuration (see mach-stm32/clock.c for details):
* - use PLL as the system clock;
* - use HSE as the PLL source;
* - configure PLL to get 216MHz system clock.
*/
#define CONFIG_STM32_SYS_CLK_PLL
#define CONFIG_STM32_PLL_SRC_HSE
#define CONFIG_STM32_HSE_HZ 25000000
#define CONFIG_STM32_PLL_M 25
#define CONFIG_STM32_PLL_N 432
#define CONFIG_STM32_PLL_P 2
#define CONFIG_STM32_PLL_Q 9
#define CONFIG_STM32_PLL_R 2
/*
* Number of clock ticks in 1 sec
*/
#define CONFIG_SYS_HZ 1000
/*
* Enable/disable h/w watchdog
*/
#undef CONFIG_HW_WATCHDOG
/*
* No interrupts
*/
#undef CONFIG_USE_IRQ
/*
* Cache configuration
*/
#define CONFIG_SYS_CACHELINE_SIZE 32
#define CONFIG_STM32F7_ICACHE_ON
#define CONFIG_STM32F7_DCACHE_ON
/*
* Actually we don't need DMAMEM if DCACHE is off. But we
* want to be able to run the same kernel image with or
* without DCACHE. So, pass a DMAMEM tag to the kernel unconditionally.
* Note, SZ_ALL must be power of 2 (to program MPU correctly)!
*/
#define CONFIG_DMAMEM
#if defined(CONFIG_DMAMEM)
# define CONFIG_DMAMEM_SZ_ALL (1 << 20) /* 1MB */
# define CONFIG_DMAMEM_SZ_FB (640 * 1024)
# define CONFIG_DMAMEM_BASE (CONFIG_SYS_RAM_BASE + \
(CONFIG_SYS_RAM_SIZE / 2) - \
CONFIG_DMAMEM_SZ_ALL)
#endif
#define CONFIG_ARMCORTEXM3_SOC_INIT
/*
* Memory layout configuration
*
* On-chip Flash:
*/
#define CONFIG_MEM_NVM_BASE 0x08000000
#define CONFIG_MEM_NVM_LEN (1024 * 1024 * 2)
#define CONFIG_ENVM 1
#if defined(CONFIG_ENVM)
# define CONFIG_SYS_ENVM_BASE 0x08000000
# define CONFIG_SYS_ENVM_LEN CONFIG_MEM_NVM_LEN
#endif
/*
* On-chip SRAM:
*/
#define CONFIG_MEM_RAM_BASE 0x20000000
#define CONFIG_MEM_RAM_LEN (20 * 1024)
#define CONFIG_MEM_RAM_BUF_LEN (88 * 1024)
#define CONFIG_MEM_MALLOC_LEN (16 * 1024)
#define CONFIG_MEM_STACK_LEN (4 * 1024)
/*
* malloc() pool size
*/
#define CONFIG_SYS_MALLOC_LEN CONFIG_MEM_MALLOC_LEN
#define FSMC_NOR_PSRAM_CS_ADDR(n) (0x60000000 + ((n) - 1) * 0x4000000)
/*
* Configuration of the external SDRAM memory
*/
#define CONFIG_NR_DRAM_BANKS 1
#define CONFIG_SYS_RAM_SIZE (16 * 1024 * 1024)
#define CONFIG_SYS_RAM_FREQ_DIV 2
#define CONFIG_SYS_RAM_BASE 0xC0000000
#define CONFIG_SYS_NO_FLASH
/*
* Store env in Flash memory
*/
#define CONFIG_ENV_IS_IN_ENVM
#define CONFIG_ENV_SIZE (4 * 1024)
#define CONFIG_ENV_ADDR (CONFIG_SYS_ENVM_BASE + (128 * 1024))
#define CONFIG_INFERNO 1
#define CONFIG_ENV_OVERWRITE 1
/*
* Serial console configuration
*/
#define CONFIG_STM32_USART_CONSOLE
/*
* USART6, TX PC.6, RX PC.7
*/
#define CONFIG_STM32_USART_PORT 6 /* USART6 */
#define CONFIG_STM32_USART_TX_IO_PORT 2 /* PORTC */
#define CONFIG_STM32_USART_TX_IO_PIN 6 /* GPIO6 */
#define CONFIG_STM32_USART_RX_IO_PORT 2 /* PORTC */
#define CONFIG_STM32_USART_RX_IO_PIN 7 /* GPIO7 */
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
/*
* Ethernet configuration
*/
#define CONFIG_NET_MULTI
#define CONFIG_STM32_ETH
#define CONFIG_STM32_ETH_RMII
/*
* Ethernet RX buffers are malloced from the internal SRAM (more precisely,
* from CONFIG_SYS_MALLOC_LEN part of it). Each RX buffer has size of 1536B.
* So, keep this in mind when changing the value of the following config,
* which determines the number of ethernet RX buffers (number of frames which
* may be received without processing until overflow happens).
*/
#define CONFIG_SYS_RX_ETH_BUFFER 4
/*
* Console I/O buffer size
*/
#define CONFIG_SYS_CBSIZE 256
/*
* Print buffer size
*/
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_RAM_BASE
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_RAM_BASE + \
CONFIG_SYS_RAM_SIZE)
/*
* Needed by "loadb"
*/
#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_RAM_BASE
/*
* Monitor is actually in eNVM. In terms of U-Boot, it is neither "flash",
* not RAM, but CONFIG_SYS_MONITOR_BASE must be defined.
*/
#define CONFIG_SYS_MONITOR_BASE 0x0
/*
* Monitor is not in flash. Need to define this to prevent
* U-Boot from running flash_protect() on the monitor code.
*/
#define CONFIG_MONITOR_IS_IN_RAM 1
#undef CONFIG_LCD
/*
* Enable all those monitor commands that are needed
*/
#include <config_cmd_default.h>
#undef CONFIG_CMD_BOOTD
#undef CONFIG_CMD_CONSOLE
#undef CONFIG_CMD_ECHO
#undef CONFIG_CMD_EDITENV
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_IMI
#undef CONFIG_CMD_ITEST
#undef CONFIG_CMD_IMLS
#undef CONFIG_CMD_LOADS
#undef CONFIG_CMD_MISC
#define CONFIG_CMD_NET
#undef CONFIG_CMD_NFS
#undef CONFIG_CMD_SOURCE
#undef CONFIG_CMD_XIMG
#undef CONFIG_CMD_BUFCOPY
/*
* To save memory disable long help
*/
#undef CONFIG_SYS_LONGHELP
/*
* Max number of command args
*/
#define CONFIG_SYS_MAXARGS 16
/*
* Auto-boot sequence configuration
*/
#define CONFIG_BOOTDELAY 1
#define CONFIG_ZERO_BOOTDELAY_CHECK
#define CONFIG_BOOTCOMMAND "run netboot"
/* boot args and env */
#define CONFIG_HOSTNAME stm32f769i-disco
#define CONFIG_BOOTARGS "stm32_platform=stm32f769i-disco " \
"console=ttyS5,115200 panic=10"
/*
* These are the good addresses to get Image data right at the 'Load Address'
* (0xC0008000), and thus avoid additional uImage relocation:
* - linux-2.6: 0xC0007FC0 (reserve place for uImage header)
* - linux-4.2: 0xC0007FB4 (reserve place for 2-files multi-image header)
*/
#define LOADADDR "0xC0007FB4"
#define REV_EXTRA_ENV \
"envmboot=run args addip;bootm ${envmaddr}\0" \
"envmupdate=tftp ${image};" \
"cptf ${envmaddr} ${loadaddr} ${filesize}\0"
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
/*
* Short-cuts to some useful commands (macros)
*/
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=" LOADADDR "\0" \
"args=setenv bootargs " CONFIG_BOOTARGS "\0" \
"addip=setenv bootargs ${bootargs}" \
" ip=${ipaddr}:${serverip}:${gatewayip}:" \
"${netmask}:${hostname}:eth0:off\0" \
"envmaddr=08040000\0" \
"ethaddr=C0:B1:3C:88:88:85\0" \
"ipaddr=172.17.4.206\0" \
"serverip=172.17.0.19\0" \
"image=stm32f7/f769i-disco.uImage\0" \
"stdin=serial\0" \
"netboot=tftp ${image}; run args addip; bootm\0" \
REV_EXTRA_ENV
/*
* Linux kernel boot parameters configuration
*/
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_CMDLINE_TAG
/*
* Enable support for booting with FDT
*/
#define CONFIG_OF_LIBFDT
#define CONFIG_OF_FORCE_RELOCATE
#define CONFIG_SYS_BOOTMAPSZ CONFIG_SYS_RAM_SIZE
#endif /* __CONFIG_H */
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