Commit 9d506483 authored by Alexander Potashev's avatar Alexander Potashev

RT106080. stm32: Set up IOMUX for LCD on STM-SOM and STM32F7-SOM

parent 60c34233
/*
* (C) Copyright 2011, 2012, 2013
* (C) Copyright 2011, 2012, 2013, 2015
*
* Yuri Tikhonov, Emcraft Systems, yur@emcraft.com
* Alexander Potashev, Emcraft Systems, aspotashev@emcraft.com
......@@ -191,6 +191,124 @@ static const struct stm32f2_gpio_dsc ext_ram_fsmc_fmc_gpio[] = {
#endif
};
#ifdef CONFIG_VIDEO_STM32F4_LTDC
static const struct stm32f2_gpio_dsc ltdc_iomux[] = {
#if defined(CONFIG_SYS_STM32F7)
/*
* STM32F7-SOM
*/
/* PI14 = LCD_CLK */
{STM32F2_GPIO_PORT_I, STM32F2_GPIO_PIN_14},
/* PK7 = LCD_DE */
{STM32F2_GPIO_PORT_K, STM32F2_GPIO_PIN_7},
/* PI12 = LCD_HSYNC */
{STM32F2_GPIO_PORT_I, STM32F2_GPIO_PIN_12},
/* PI13 = LCD_VSYNC */
{STM32F2_GPIO_PORT_I, STM32F2_GPIO_PIN_13},
/* PJ12 = LCD_B0 */
{STM32F2_GPIO_PORT_J, STM32F2_GPIO_PIN_12},
/* PJ13 = LCD_B1 */
{STM32F2_GPIO_PORT_J, STM32F2_GPIO_PIN_13},
/* PJ14 = LCD_B2 */
{STM32F2_GPIO_PORT_J, STM32F2_GPIO_PIN_14},
/* PJ15 = LCD_B3 */
{STM32F2_GPIO_PORT_J, STM32F2_GPIO_PIN_15},
/* PK3 = LCD_B4 */
{STM32F2_GPIO_PORT_K, STM32F2_GPIO_PIN_3},
/* PK4 = LCD_B5 */
{STM32F2_GPIO_PORT_K, STM32F2_GPIO_PIN_4},
/* PK5 = LCD_B6 */
{STM32F2_GPIO_PORT_K, STM32F2_GPIO_PIN_5},
/* PK6 = LCD_B7 */
{STM32F2_GPIO_PORT_K, STM32F2_GPIO_PIN_6},
/* PJ7 = LCD_G0 */
{STM32F2_GPIO_PORT_J, STM32F2_GPIO_PIN_7},
/* PJ8 = LCD_G1 */
{STM32F2_GPIO_PORT_J, STM32F2_GPIO_PIN_8},
/* PJ9 = LCD_G2 */
{STM32F2_GPIO_PORT_J, STM32F2_GPIO_PIN_9},
/* PJ10 = LCD_G3 */
{STM32F2_GPIO_PORT_J, STM32F2_GPIO_PIN_10},
/* PJ11 = LCD_G4 */
{STM32F2_GPIO_PORT_J, STM32F2_GPIO_PIN_11},
/* PK0 = LCD_G5 */
{STM32F2_GPIO_PORT_K, STM32F2_GPIO_PIN_0},
/* PK1 = LCD_G6 */
{STM32F2_GPIO_PORT_K, STM32F2_GPIO_PIN_1},
/* PK2 = LCD_G7 */
{STM32F2_GPIO_PORT_K, STM32F2_GPIO_PIN_2},
/* PI15 = LCD_R0 */
{STM32F2_GPIO_PORT_I, STM32F2_GPIO_PIN_15},
/* PJ0 = CD_R1 */
{STM32F2_GPIO_PORT_J, STM32F2_GPIO_PIN_0},
/* PJ1 = LCD_R2 */
{STM32F2_GPIO_PORT_J, STM32F2_GPIO_PIN_1},
/* PJ2 = LCD_R3 */
{STM32F2_GPIO_PORT_J, STM32F2_GPIO_PIN_2},
/* PJ3 = LCD_R4 */
{STM32F2_GPIO_PORT_J, STM32F2_GPIO_PIN_3},
/* PJ4 = LCD_R5 */
{STM32F2_GPIO_PORT_J, STM32F2_GPIO_PIN_4},
/* PJ5 = LCD_R6 */
{STM32F2_GPIO_PORT_J, STM32F2_GPIO_PIN_5},
/* PJ6 = LCD_R7 */
{STM32F2_GPIO_PORT_J, STM32F2_GPIO_PIN_6},
#else
/*
* STM-SOM
*/
/* PG7 = LCD_CLK */
{STM32F2_GPIO_PORT_G, STM32F2_GPIO_PIN_7},
/* PF10 = LCD_DE */
{STM32F2_GPIO_PORT_F, STM32F2_GPIO_PIN_10},
/* PI10 = LCD_HSYNC */
{STM32F2_GPIO_PORT_I, STM32F2_GPIO_PIN_10},
/* PI9 = LCD_VSYNC */
{STM32F2_GPIO_PORT_I, STM32F2_GPIO_PIN_9},
/* PG12 = LCD_B1 */
{STM32F2_GPIO_PORT_G, STM32F2_GPIO_PIN_12},
/* PG10 = LCD_B2 */
{STM32F2_GPIO_PORT_G, STM32F2_GPIO_PIN_10},
/* PI4 = LCD_B4 */
{STM32F2_GPIO_PORT_I, STM32F2_GPIO_PIN_4},
/* PI5 = LCD_B5 */
{STM32F2_GPIO_PORT_I, STM32F2_GPIO_PIN_5},
/* PI6 = LCD_B6 */
{STM32F2_GPIO_PORT_I, STM32F2_GPIO_PIN_6},
/* PI7 = LCD_B7 */
{STM32F2_GPIO_PORT_I, STM32F2_GPIO_PIN_7},
/* PH13 = LCD_G2 */
{STM32F2_GPIO_PORT_H, STM32F2_GPIO_PIN_13},
/* PH14 = LCD_G3 */
{STM32F2_GPIO_PORT_H, STM32F2_GPIO_PIN_14},
/* PH15 = LCD_G4 */
{STM32F2_GPIO_PORT_H, STM32F2_GPIO_PIN_15},
/* PI0 = LCD_G5 */
{STM32F2_GPIO_PORT_I, STM32F2_GPIO_PIN_0},
/* PC7 = LCD_G6 */
{STM32F2_GPIO_PORT_C, STM32F2_GPIO_PIN_7},
/* PI2 = LCD_G7 */
{STM32F2_GPIO_PORT_I, STM32F2_GPIO_PIN_2},
/* PH2 = LCD_R0 */
{STM32F2_GPIO_PORT_H, STM32F2_GPIO_PIN_2},
/* PH3 = LCD_R1 */
{STM32F2_GPIO_PORT_H, STM32F2_GPIO_PIN_3},
/* PH8 = LCD_R2 */
{STM32F2_GPIO_PORT_H, STM32F2_GPIO_PIN_8},
/* PH9 = LCD_R3 */
{STM32F2_GPIO_PORT_H, STM32F2_GPIO_PIN_9},
/* PH10 = LCD_R4 */
{STM32F2_GPIO_PORT_H, STM32F2_GPIO_PIN_10},
/* PH11 = LCD_R5 */
{STM32F2_GPIO_PORT_H, STM32F2_GPIO_PIN_11},
/* PH12 = LCD_R6 */
{STM32F2_GPIO_PORT_H, STM32F2_GPIO_PIN_12},
/* PG6 = LCD_R7 */
{STM32F2_GPIO_PORT_G, STM32F2_GPIO_PIN_6},
#endif
};
#endif /* CONFIG_VIDEO_STM32F4_LTDC */
/*
* Init FMC/FSMC GPIOs based
*/
......@@ -214,6 +332,29 @@ out:
return rv;
}
#ifdef CONFIG_VIDEO_STM32F4_LTDC
/*
* Initialize LCD pins
*/
static int ltdc_setup_iomux(void)
{
int rv = 0;
int i;
/*
* Connect GPIOs to FMC controller
*/
for (i = 0; i < ARRAY_SIZE(ltdc_iomux); i++) {
rv = stm32f2_gpio_config(&ltdc_iomux[i],
STM32F2_GPIO_ROLE_LTDC);
if (rv)
break;
}
return rv;
}
#endif /* CONFIG_VIDEO_STM32F4_LTDC */
/*
* Early hardware init.
*/
......@@ -272,6 +413,12 @@ int board_init(void)
#endif
#endif
#ifdef CONFIG_VIDEO_STM32F4_LTDC
rv = ltdc_setup_iomux();
if (rv)
return rv;
#endif /* CONFIG_VIDEO_STM32F4_LTDC */
return 0;
}
......
......@@ -101,6 +101,11 @@ DECLARE_GLOBAL_DATA_PTR;
*/
#define STM32F2_GPIO_AF_FSMC 0x0C
/*
* LTDC AF
*/
#define STM32F2_GPIO_AF_LTDC 0x0E
/*
* GPIO register map
*/
......@@ -134,6 +139,7 @@ static const u32 af_val[STM32F2_GPIO_ROLE_LAST] = {
STM32F2_GPIO_AF_USART4, STM32F2_GPIO_AF_USART5, STM32F2_GPIO_AF_USART6,
STM32F2_GPIO_AF_MAC,
(u32)-1,
STM32F2_GPIO_AF_LTDC,
STM32F2_GPIO_AF_FSMC,
(u32)-1
};
......@@ -192,6 +198,12 @@ s32 stm32f2_gpio_config(const struct stm32f2_gpio_dsc *dsc,
pupd = STM32F2_GPIO_PUPD_NO;
mode = STM32F2_GPIO_MODE_OUT;
break;
case STM32F2_GPIO_ROLE_LTDC:
otype = STM32F2_GPIO_OTYPE_PP;
ospeed = STM32F2_GPIO_SPEED_50M;
pupd = STM32F2_GPIO_PUPD_NO;
mode = STM32F2_GPIO_MODE_AF;
break;
default:
if (gd->have_console)
printf("%s: incorrect role %d.\n", __func__, role);
......
......@@ -73,6 +73,7 @@ enum stm32f2_gpio_role {
STM32F2_GPIO_ROLE_USART6, /* USART6 */
STM32F2_GPIO_ROLE_ETHERNET, /* MAC */
STM32F2_GPIO_ROLE_MCO, /* MC external output clock */
STM32F2_GPIO_ROLE_LTDC, /* LCD controller */
STM32F2_GPIO_ROLE_FSMC, /* FSMC static memory controller */
STM32F2_GPIO_ROLE_FMC = STM32F2_GPIO_ROLE_FSMC,
STM32F2_GPIO_ROLE_GPOUT, /* GPOUT */
......
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