Commit b6bb6ea4 authored by Sergei Poselenov's avatar Sergei Poselenov

RT #80404. M2S-SOM support (merge from draft tree).

Supported:
 - UART0 (57600)
 - SPI0 (non-DMA)
 - Ethernet
 - LPDDR
 - Env in SPI Flash
parent 330d3552
......@@ -3245,6 +3245,12 @@ lpc4350-eval_config : unconfig
lpc1850-eval_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm_cortexm3 lpc1850-eval hitex lpc18xx
m2s-som_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm_cortexm3 m2s-som emcraft m2s
m2s-som-copy2_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm_cortexm3 m2s-som emcraft m2s
#########################################################################
## XScale Systems
#########################################################################
......
#
# (C) Copyright 2010, 2011
# Vladimir Khusainov, Emcraft Systems, vlad@emcraft.com
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS := board.o
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
$(LIB): $(obj).depend $(OBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
/*
* board/emcraft/m2s-som/board.c
*
* Board specific code the the Emcraft SmartFusion2 system-on-module (SOM).
*
* (C) Copyright 2012
* Emcraft Systems, <www.emcraft.com>
* Alexander Potashev <aspotashev@emcraft.com>
* Vladimir Khusainov <vlad@emcraft.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <netdev.h>
#include <asm/arch/ddr.h>
/*
* TBD: move to config or convert at run-time?
* Generate DDR timings depending on the following DDR clock
*/
#define M2S_DDR_MHZ 160
/*
* Common conversion macros used for DDR cfg
*/
#define M2S_CLK_VAL(ns, div) ((((ns) * M2S_DDR_MHZ) / div))
#define M2S_CLK_MOD(ns, div) ((((ns) * M2S_DDR_MHZ) % div))
#define M2S_CLK_MIN(ns) (M2S_CLK_MOD(ns,1000) ? \
M2S_CLK_VAL(ns,1000) + 1 : \
M2S_CLK_VAL(ns,1000))
#define M2S_CLK32_MIN(ns) (M2S_CLK_MOD(ns,32000) ? \
M2S_CLK_VAL(ns,32000) + 1 : \
M2S_CLK_VAL(ns,32000))
#define M2S_CLK1024_MIN(ns) (M2S_CLK_MOD(ns,1024000) ? \
M2S_CLK_VAL(ns,1024000) + 1 : \
M2S_CLK_VAL(ns,1024000))
#define M2S_CLK_MAX(ns) (M2S_CLK_VAL(ns,1000))
#define M2S_CLK32_MAX(ns) (M2S_CLK_VAL(ns,32000))
#define M2S_CLK1024_MAX(ns) (M2S_CLK_VAL(ns,1024000))
/*
* MT46H32M16LFBF-6 params & timings
*/
#define DDR_BL 16 /* Burst length (value) */
#define DDR_MR_BL 4 /* Burst length (power of 2) */
#define DDR_BT 0 /* Burst type int(1)/seq(0) */
#define DDR_CL 3 /* CAS (read) latency */
#define DDR_WL 1 /* Write latency */
#define DDR_tMRD 2
#define DDR_tWTR 1
#define DDR_tXP 1
#define DDR_tCKE 1
#define DDR_tRFC M2S_CLK_MIN(72)
#define DDR_tREFI M2S_CLK32_MAX(15600)
#define DDR_tCKE_pre M2S_CLK1024_MIN(200000)
#define DDR_tCKE_post M2S_CLK1024_MIN(400)
#define DDR_tRCD M2S_CLK_MIN(18)
#define DDR_tRRD M2S_CLK_MIN(12)
#define DDR_tRP M2S_CLK_MIN(18)
#define DDR_tRC M2S_CLK_MIN(60)
#define DDR_tRAS_max M2S_CLK1024_MAX(70000)
#define DDR_tRAS_min M2S_CLK_MIN(42)
#define DDR_tWR M2S_CLK_MIN(15)
/*
* There are no these timings exactly in spec, so take smth
*/
#define DDR_tCCD 2 /* 2-reads/writes (bank A to B) */
DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
{
return 0;
}
int checkboard(void)
{
printf("Board: M2S-SOM Rev %s, www.emcraft.com\n",
CONFIG_SYS_BOARD_REV_STR);
return 0;
}
/*
* Initialize DRAM
*/
int dram_init (void)
{
#if ( CONFIG_NR_DRAM_BANKS > 0 )
volatile struct ddr_regs *ddr = (void *)0x40020000;
u16 val;
/*
* Enable access to MDDR regs
*/
M2S_SYSREG->mddr_cr = (1 << 0);
/*
* Configure mode, and mapping:
* - LPDDR1 + PHY-16 + ECC_DISABLE
* - BANK:1-0,COL:9-0,ROW:12-0 <-> src[2]..
*/
ddr->ddrc.DYN_POWERDOWN_CR = (0 << REG_DDRC_POWERDOWN_EN);
ddr->ddrc.MODE_CR = ( 1 << REG_DDRC_MOBILE) |
( 1 << REG_DDRC_SDRAM) |
(0x1 << REG_DDRC_DATA_BUS_WIDTH);
ddr->ddrc.ADDR_MAP_BANK_CR = 0x099F;
ddr->ddrc.ADDR_MAP_COL_1_CR = 0x3333;
ddr->ddrc.ADDR_MAP_COL_2_CR = 0xFFFF;
ddr->ddrc.ADDR_MAP_COL_3_CR = 0x3300;
ddr->ddrc.ADDR_MAP_ROW_1_CR = 0x7777;
ddr->ddrc.ADDR_MAP_ROW_2_CR = 0x0FFF;
/*
* Setup timings
*/
ddr->ddrc.DYN_REFRESH_1_CR = (DDR_tRFC << REG_DDRC_T_RFC_MIN) |
(1 << REG_DDRC_SELFREF_EN);
ddr->ddrc.DYN_REFRESH_2_CR = (DDR_tREFI << REG_DDRC_T_RFC_NOM_X32);
ddr->ddrc.CKE_RSTN_CYCLES_1_CR = DDR_tCKE_pre << REG_DDRC_PRE_CKE_X1024;
ddr->ddrc.CKE_RSTN_CYCLES_2_CR = DDR_tCKE_post << REG_DDRC_POST_CKE_X1024;
ddr->ddrc.DRAM_BANK_ACT_TIMING_CR = (DDR_tRCD << REG_DDRC_T_RCD) |
(DDR_tCCD << REG_DDRC_T_CCD) |
(DDR_tRRD << REG_DDRC_T_RRD) |
(DDR_tRP << REG_DDRC_T_RP);
ddr->ddrc.DRAM_BANK_TIMING_PARAM_CR = DDR_tRC << REG_DDRC_T_RC;
ddr->ddrc.DRAM_MR_TIMING_PARAM_CR = DDR_tMRD << REG_DDRC_T_MRD;
ddr->ddrc.DRAM_RAS_TIMING_CR = (DDR_tRAS_max << REG_DDRC_T_RAS_MAX) |
(DDR_tRAS_min << REG_DDRC_T_RAS_MIN);
ddr->ddrc.DFI_RDDATA_EN_CR = DDR_CL << REG_DDRC_DFI_T_RDDATA_EN;
ddr->ddrc.DRAM_RD_WR_LATENCY_CR = (DDR_WL << REG_DDRC_WRITE_LATENCY) |
(DDR_CL << REG_DDRC_READ_LATENCY);
/*
* DDR Mode register values
* - Burst Length, CL, and BT=Interleaved
* - Drive Strength 1/2
*/
val = (DDR_CL << 4) | (DDR_BT << 3) | (DDR_MR_BL << 0);
ddr->ddrc.INIT_MR_CR = val;
ddr->ddrc.INIT_EMR_CR = 0x0020;
ddr->ddrc.MODE_REG_DATA_CR = val;
ddr->ddrc.MODE_REG_RD_WR_CR = 1 << 3;
/*
* Configure BL16, and related timings
*/
ddr->ddrc.PERF_PARAM_1_CR = ((DDR_BL >> 2) << REG_DDRC_BURST_RDWR);
ddr->ddrc.PERF_PARAM_2_CR = (DDR_BT << REG_DDRC_BURST_MODE);
ddr->ddrc.DRAM_RD_WR_TRNARND_TIME_CR = ((DDR_CL + (DDR_BL/2) + 2 -
DDR_WL) << REG_DDRC_RD2WR) |
((DDR_WL + DDR_tWTR +
(DDR_BL/2)) << REG_DDRC_WR2RD);
ddr->ddrc.DRAM_RD_WR_PRE_CR = ((DDR_WL + (DDR_BL/2) +
DDR_tWR) << REG_DDRC_WR2PRE) |
((DDR_BL/2) << REG_DDRC_RD2PRE);
ddr->ddrc.DRAM_T_PD_CR = (DDR_tXP << REG_DDRC_T_XP) |
(DDR_tCKE << REG_DDRC_T_CKE);
/*
* Queue params
* FIXME: clean-up these somehow
*/
ddr->ddrc.HPR_QUEUE_PARAM_1_CR = 0x80F8;
ddr->ddrc.HPR_QUEUE_PARAM_2_CR = 0x0007;
ddr->ddrc.LPR_QUEUE_PARAM_1_CR = 0x80F8;
ddr->ddrc.LPR_QUEUE_PARAM_2_CR = 0x0007;
ddr->ddrc.WR_QUEUE_PARAM_CR = 0x0200;
/*
* PHY Registers
* FIXME: clean-up these somehow
*/
ddr->phy.DYN_LOOPBACK_TEST_CR = 0x0000;
ddr->phy.CTRL_SLAVE_RATIO_CR = 0x0080;
ddr->phy.DATA_SLICE_IN_USE_CR = 0x000F;
ddr->phy.DLL_LOCK_DIFF_CR = 0x000B;
ddr->phy.FIFO_WE_SLAVE_RATIO_1_CR = 0x0000;
ddr->phy.FIFO_WE_SLAVE_RATIO_2_CR = 0x0000;
ddr->phy.FIFO_WE_SLAVE_RATIO_3_CR = 0x0000;
ddr->phy.FIFO_WE_SLAVE_RATIO_4_CR = 0x0000;
ddr->phy.LOCAL_ODT_CR = 0x0001;
ddr->phy.RD_DQS_SLAVE_RATIO_1_CR = 0x0040;
ddr->phy.RD_DQS_SLAVE_RATIO_2_CR = 0x0401;
ddr->phy.RD_DQS_SLAVE_RATIO_3_CR = 0x4010;
ddr->phy.WR_DATA_SLAVE_RATIO_1_CR = 0x0040;
ddr->phy.WR_DATA_SLAVE_RATIO_2_CR = 0x0401;
ddr->phy.WR_DATA_SLAVE_RATIO_3_CR = 0x4010;
ddr->phy.WR_RD_RL_CR = 0x0000;
ddr->phy.RDC_WE_TO_RE_DELAY_CR = 0x0003;
ddr->phy.USE_FIXED_RE_CR = 0x0001;
ddr->phy.USE_RANK0_DELAYS_CR = 0x0001;
ddr->phy.DYN_CONFIG_CR = 0x0009;
ddr->phy.DQ_OFFSET_1_CR = 0x0000;
ddr->phy.DQ_OFFSET_2_CR = 0x0000;
ddr->phy.DYN_RESET_CR = 0x0001;
ddr->ddrc.DYN_SOFT_RESET_CR = 0x0001;
/*
* Fill in global info with description of SRAM configuration.
*/
gd->bd->bi_dram[0].start = CONFIG_SYS_RAM_BASE;
gd->bd->bi_dram[0].size = CONFIG_SYS_RAM_SIZE;
#endif
return 0;
}
int misc_init_r(void)
{
return 0;
}
#ifdef CONFIG_M2S_ETH
int board_eth_init(bd_t *bis)
{
return m2s_eth_driver_init(bis);
}
#endif
......@@ -22,7 +22,6 @@
#
PLATFORM_CPPFLAGS += -DCONFIG_MEM_NVM_BASE=$(CONFIG_MEM_NVM_BASE)
PLATFORM_CPPFLAGS += -DCONFIG_MEM_NVM_LEN=$(CONFIG_MEM_NVM_LEN)
PLATFORM_CPPFLAGS += -DCONFIG_MEM_NVM_UBOOT_OFF=$(CONFIG_MEM_NVM_UBOOT_OFF)
PLATFORM_CPPFLAGS += -DCONFIG_MEM_NVM_UBOOT_OFF=$(if $(CONFIG_MEM_NVM_UBOOT_OFF),$(CONFIG_MEM_NVM_UBOOT_OFF),0x0)
PLATFORM_CPPFLAGS += -DCONFIG_MEM_RAM_BASE=$(CONFIG_MEM_RAM_BASE)
PLATFORM_CPPFLAGS += -DCONFIG_MEM_RAM_LEN=$(CONFIG_MEM_RAM_LEN)
......
......@@ -64,6 +64,8 @@ int arch_cpu_init(void)
gd->bd->bi_arch_number = MACH_TYPE_LPC18XX;
#elif defined(CONFIG_SYS_KINETIS)
gd->bd->bi_arch_number = MACH_TYPE_KINETIS;
#elif defined(CONFIG_SYS_M2S)
gd->bd->bi_arch_number = MACH_TYPE_M2S;
#else
# error "Unsupported Cortex-M3 SOC."
#endif
......
#
# (C) Copyright 2000-2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2012
# Port to M2S (Actel SmartFusion2)
# Alexander Potashev, Emcraft Systems, aspotashev@emcraft.com.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).a
COBJS-$(CONFIG_CMD_SOMTEST) += cmd_somtest.o
COBJS-$(CONFIG_CMD_A2F_SPI_TEST) += cmd_spitest.o
COBJS-$(CONFIG_ARMCORTEXM3_SOC_INIT) += soc.o
COBJS := clock.o cpu.o envm.o wdt.o $(COBJS-y)
SRCS := $(COBJS:.o=.c) $(SOBJS:.o=.s)
OBJS := $(addprefix $(obj),$(COBJS))
$(LIB): $(obj).depend $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean:
rm -f $(LIB) core *.bak $(obj).depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################
/*
* Copyright (C) 2012
* Alexander Potashev, Emcraft Systems, aspotashev@emcraft.com
* Vladimir Khusainov, Emcraft Systems, vlad@emcraft.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <common.h>
#include <asm/io.h>
#include "clock.h"
/*
* Array of various reference clocks
*/
static unsigned long clock[CLOCK_END];
/*
* Kick-off the MPLL of SmartFusion2
*/
static void clock_mss_init(void)
{
/*
* Check if PERSIST_CC is set. If it is, it means that
* FACC is in reset and its registers hasn't initialized yet.
* The workaround is to de-assert the reset and perform
* the software reset making FACC initialize properly.
*/
if (M2S_SYSREG->mssddr_facc1_cr & (1<<25)) {
M2S_SYSREG->mssddr_facc1_cr &= ~(1<<25);
reset_cpu(0);
}
/*
* Analog voltage = 3.3v. Libero appears to ignore this
* setting and defines this as 2.5v regardless.
* We change it dynamically.
*/
M2S_SYSREG->mssddr_pll_status_high_cr &= ~(1<<2);
/*
* Wait for fabric PLL to lock. MPPL is getting clock from FPGA PLL.
*/
while (!(M2S_SYSREG->mssddr_pll_status & (1<<0)));
/*
* Negate MPLL bypass.
*/
M2S_SYSREG->mssddr_pll_status_high_cr &= ~(1<<0);
/*
* Wait for MPLL to lock.
*/
while (!(M2S_SYSREG->mssddr_pll_status & (1<<1)));
/*
* Drive M3, PCLK0, PCLK1 from stage 2 dividers.
* This is what enables the MPLL.
*/
M2S_SYSREG->mssddr_facc1_cr &= ~(1<<12);
}
/*
* Calculate the divisor for a specified FACC1 field
* @param r FACC1 value
* @param s FACC1 divisor field
* @returns divisor
*/
static unsigned int clock_mss_divisor(unsigned int r, unsigned int s)
{
unsigned int v, ret;
/*
* Get a 3-bit field that defines the divisor
*/
v = (r & (0x7<<s)) >> s;
/*
* Translate the bit representation of the divisor to
* a value ready to be used in calculation of a clock.
*/
switch (v) {
case 0: ret = 1; break;
case 1: ret = 2; break;
case 2: ret = 4; break;
case 4: ret = 8; break;
case 5: ret = 16; break;
case 6: ret = 32; break;
default: ret = 1; break;
}
return ret;
}
/*
* Perform reference clocks learning
*/
static void clock_mss_learn(void)
{
unsigned int r1 = M2S_SYSREG->mssddr_facc1_cr;
unsigned int r2 = M2S_SYSREG->mssddr_pll_status_low_cr;
/*
* System reference clock is defined as a build-time constant.
* This clock comes from the FPGA PLL and we can't determine
* its value at run time. All clocks derived from CLK_BASE
* can be calculated at run time (and we do just that).
*/
clock[CLOCK_SYSREF] = CONFIG_SYS_M2S_SYSREF;
/*
* Respectively:
* M3_CLK_DIVISOR
* DDR
* APB0_DIVISOR
* APB1_DIVISOR
* FIC32_0_DIVISOR
*/
clock[CLOCK_SYSTICK] = clock[CLOCK_SYSREF] / clock_mss_divisor(r1, 9);
clock[CLOCK_DDR] = clock[CLOCK_SYSREF] / clock_mss_divisor(r2, 16);
clock[CLOCK_PCLK0] = clock[CLOCK_SYSREF] / clock_mss_divisor(r1, 2);
clock[CLOCK_PCLK1] = clock[CLOCK_SYSREF] / clock_mss_divisor(r1, 5);
clock[CLOCK_FPGA] = clock[CLOCK_SYSREF] / clock_mss_divisor(r1, 13);
}
/*
* Initialize the various clocks
*/
void clock_init(void)
{
/*
* Initialize the MSS MPLL/CCC
*/
clock_mss_init();
/*
* Perform clock learning.
*/
clock_mss_learn();
}
/*
* Get the value of a specified reference clock
* @param clck reference clock
* @returns value of the clock
*/
ulong clock_get(enum clock clck)
{
ulong res = 0;
if (clck >= 0 && clck < CLOCK_END) {
res = clock[clck];
}
return res;
}
/*
* (C) Copyright 2012
* Vladimir Khusainov, Emcraft Systems, vlad@emcraft.com
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <command.h>
#include <string.h>
#include "envm.h"
extern void a2f_spi_test(unsigned int bus, unsigned int cmd);
/*
* Run SPI test
*/
int do_spitest(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
unsigned int bus;
unsigned int cmd;
int ret = 0;
/*
* Check that the call has the right # of parameters
*/
if (argc < 3) {
printf("%s: bus number and command must be specified\n",
(char *) argv[0]);
goto Done;
}
/*
* Parse and validate command arguments
*/
bus = simple_strtoul(argv[1], NULL, 16);
if (bus != 0 && bus != 1 && bus != 2) {
printf("%s: bus number must be 0, 1 or 2\n", (char *) argv[0]);
goto Done;
}
cmd = simple_strtoul(argv[2], NULL, 16);
/*
* Call the SPI driver in order to run actual test
*/
a2f_spi_test(bus, cmd);
Done:
return ret;
}
U_BOOT_CMD(
spitest, 5, 0, do_spitest,
"Run SPI test",
"bus"
);
/*
* (C) Copyright 2012
* Alexander Potashev, Emcraft Systems, aspotashev@emcraft.com
* Vladimir Khusainov, Emcraft Systems, vlad@emcraft.com
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include "clock.h"
/*
* Print the CPU specific information
*/
int print_cpuinfo(void)
{
char buf[CLOCK_END][32];
printf("CPU : %s\n", "SmartFusion2 cSoC (Cortex-M3 Hard IP)");
strmhz(buf[CLOCK_SYSTICK], clock_get(CLOCK_SYSTICK));
strmhz(buf[CLOCK_DDR], clock_get(CLOCK_DDR));
strmhz(buf[CLOCK_PCLK0], clock_get(CLOCK_PCLK0));
strmhz(buf[CLOCK_PCLK1], clock_get(CLOCK_PCLK1));
printf("Freqs: CORTEX-M3=%sMHz,DDR=%sMhz,"
"PCLK0=%sMHz,PCLK1=%sMHz\n",
buf[CLOCK_SYSTICK], buf[CLOCK_DDR],
buf[CLOCK_PCLK0], buf[CLOCK_PCLK1]);
return 0;
}
/*
* (C) Copyright 2012
* Vladimir Khusainov, Emcraft Systems, vlad@emcraft.com
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include "clock.h"
/*
* The current code is good only for ENVM0.
* It needs to be updated to work with ENVM1.
* ...
* eNVM control & status registers
*/
struct mss_envm {
unsigned int reserved_0_to_80[32];
unsigned int wdbuff[32];
unsigned int reserved_100_to_120[8];
unsigned int status;
unsigned int reserved_124_to_128[1];
unsigned int nv_page_status;
unsigned int nv_freq_rng;
unsigned int nv_dpd_b;
unsigned int nv_ce;
unsigned int reserved_138_to_140[2];
unsigned int page_lock_set;
unsigned int dwsize;
unsigned int cmd;
unsigned int reserved_14c_to_154[2];
unsigned int inten;
unsigned int clrhint;
unsigned int reserved_15c_to_1fc[40];
unsigned int reqaccess;
};
/*
* eNVM registers access handle
*/
#define MSS_ENVM_REGS_BASE 0x60080000
#define MSS_ENVM ((volatile struct mss_envm *) \
(MSS_ENVM_REGS_BASE))
/*
* Base address of the eNVM Flash
*/
#define MSS_ENVM_BASE 0x60000000
/*
* eNVM Flash size.
* TO-DO: this needs to be made a function of some build-time,
* perhaps even run-time, parameter defining a SmartFusion chip model.
*/
#define MSS_ENVM_FLASH_SIZE (1024 * 256)
/*