Commit daf8b81c authored by Alexander Dyachenko's avatar Alexander Dyachenko Committed by Sergei Poselenov

RM 1947: Configure MMC and FSL_ESDHC drivers for the Ametek-2U board and...

RM 1947: Configure MMC and FSL_ESDHC drivers for the Ametek-2U board and K70-SOM, enable necessary workarounds

(cherry picked from commit d189fb147ed3b9c00306fd669685a4127b9488ee)

Conflicts:
	board/emcraft/k70-som/board.c
	include/configs/ametek-fpc.h
parent 586667b4
...@@ -26,6 +26,9 @@ ...@@ -26,6 +26,9 @@
#include <common.h> #include <common.h>
#include <netdev.h> #include <netdev.h>
#include <nand.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <asm/arch/kinetis.h> #include <asm/arch/kinetis.h>
#include <asm/arch/kinetis_gpio.h> #include <asm/arch/kinetis_gpio.h>
...@@ -422,6 +425,24 @@ static const struct kinetis_gpio_pin_config k70_som_gpio[] = { ...@@ -422,6 +425,24 @@ static const struct kinetis_gpio_pin_config k70_som_gpio[] = {
/* C.5 = NFC_D7 */ /* C.5 = NFC_D7 */
{{KINETIS_GPIO_PORT_C, 5}, KINETIS_GPIO_CONFIG_DSE(5)}, {{KINETIS_GPIO_PORT_C, 5}, KINETIS_GPIO_CONFIG_DSE(5)},
#endif /* CONFIG_CMD_NAND */ #endif /* CONFIG_CMD_NAND */
#ifdef CONFIG_FSL_ESDHC
/* E.0 = SDHC0_D1 */
{{KINETIS_GPIO_PORT_E, 0}, KINETIS_GPIO_CONFIG_MUX(4)},
/* E.1 = SDHC0_D0 */
{{KINETIS_GPIO_PORT_E, 1}, KINETIS_GPIO_CONFIG_MUX(4)},
/* E.2 = SDHC0_DCLK */
{{KINETIS_GPIO_PORT_E, 2}, KINETIS_GPIO_CONFIG_MUX(4)},
/* E.3 = SDHC0_CMD */
{{KINETIS_GPIO_PORT_E, 3}, KINETIS_GPIO_CONFIG_MUX(4)},
/* E.4 = SDHC0_D3 */
{{KINETIS_GPIO_PORT_E, 4}, KINETIS_GPIO_CONFIG_MUX(4)},
/* E.5 = SDHC0_D2 */
{{KINETIS_GPIO_PORT_E, 5}, KINETIS_GPIO_CONFIG_MUX(4)},
/* E.28 = SD switch */
{{KINETIS_GPIO_PORT_E, 28}, KINETIS_GPIO_CONFIG_PULLUP(1)},
#endif
}; };
/* /*
...@@ -899,3 +920,17 @@ int board_eth_init(bd_t *bis) ...@@ -899,3 +920,17 @@ int board_eth_init(bd_t *bis)
} }
#endif #endif
#ifdef CONFIG_FSL_ESDHC
int board_mmc_getcd(struct mmc *mmc)
{
/*
* Check GPIO E.28 for the SD card presence
*/
return (*(volatile uint *)0x400FF110 & (1 << 28)) ? 0 : 1;
}
int board_mmc_init(bd_t *bis)
{
return fsl_esdhc_mmc_init(bis);
}
#endif
...@@ -29,7 +29,7 @@ include $(TOPDIR)/config.mk ...@@ -29,7 +29,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).a LIB = $(obj)lib$(SOC).a
COBJS := clock.o cpu.o envm.o eth.o soc.o wdt.o COBJS := clock.o cpu.o envm.o eth.o soc.o wdt.o speed.o
SOBJS := SOBJS :=
SRCS := $(COBJS:.o=.c) SRCS := $(COBJS:.o=.c)
......
...@@ -125,6 +125,13 @@ void cortex_m3_soc_init(void) ...@@ -125,6 +125,13 @@ void cortex_m3_soc_init(void)
kinetis_periph_enable(KINETIS_CG_NFC, 1); kinetis_periph_enable(KINETIS_CG_NFC, 1);
#endif /* CONFIG_CMD_NAND */ #endif /* CONFIG_CMD_NAND */
#ifdef CONFIG_FSL_ESDHC
/*
* Enable the clock on the SDHC Controller module of the MCU
*/
kinetis_periph_enable(KINETIS_CG_ESDHC, 1);
#endif /* CONFIG_CMD_NAND */
/* /*
* Disable the MPU to let the Ethernet module access the SRAM * Disable the MPU to let the Ethernet module access the SRAM
*/ */
......
/*
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
int get_clocks(void)
{
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_FSL_ESDHC
gd->sdhc_clk = 120000000;
#endif
return 0;
}
...@@ -724,7 +724,12 @@ int sd_change_freq(struct mmc *mmc) ...@@ -724,7 +724,12 @@ int sd_change_freq(struct mmc *mmc)
if (mmc_host_is_spi(mmc)) if (mmc_host_is_spi(mmc))
return 0; return 0;
timeout = 3;
/* Read the SCR to find out if this card supports higher speeds */ /* Read the SCR to find out if this card supports higher speeds */
#ifdef CONFIG_MMC_RETRY_SCR_FIX
retry_scr:
#endif
cmd.cmdidx = MMC_CMD_APP_CMD; cmd.cmdidx = MMC_CMD_APP_CMD;
cmd.resp_type = MMC_RSP_R1; cmd.resp_type = MMC_RSP_R1;
cmd.cmdarg = mmc->rca << 16; cmd.cmdarg = mmc->rca << 16;
...@@ -740,9 +745,9 @@ int sd_change_freq(struct mmc *mmc) ...@@ -740,9 +745,9 @@ int sd_change_freq(struct mmc *mmc)
cmd.cmdarg = 0; cmd.cmdarg = 0;
cmd.flags = 0; cmd.flags = 0;
timeout = 3; #ifndef CONFIG_MMC_RETRY_SCR_FIX
retry_scr: retry_scr:
#endif
data.dest = (char *)scr; data.dest = (char *)scr;
data.blocksize = 8; data.blocksize = 8;
data.blocks = 1; data.blocks = 1;
......
...@@ -93,6 +93,8 @@ typedef u32 kinetis_clock_gate_t; ...@@ -93,6 +93,8 @@ typedef u32 kinetis_clock_gate_t;
#define KINETIS_CG_DDR KINETIS_MKCG(2, 14) /* SIM_SCGC3[14] */ #define KINETIS_CG_DDR KINETIS_MKCG(2, 14) /* SIM_SCGC3[14] */
/* NAND Flash Controller */ /* NAND Flash Controller */
#define KINETIS_CG_NFC KINETIS_MKCG(2, 8) /* SIM_SCGC3[8] */ #define KINETIS_CG_NFC KINETIS_MKCG(2, 8) /* SIM_SCGC3[8] */
/* ESDHC Controller */
#define KINETIS_CG_ESDHC KINETIS_MKCG(2, 17) /* SIM_SCGC3[8] */
/* OSC1 */ /* OSC1 */
#define KINETIS_CG_OSC1 KINETIS_MKCG(0, 5) /* SIM_SCGC1[5] */ #define KINETIS_CG_OSC1 KINETIS_MKCG(0, 5) /* SIM_SCGC1[5] */
/* RTC */ /* RTC */
......
...@@ -30,6 +30,9 @@ ...@@ -30,6 +30,9 @@
/* Pull Enable (pull-down by default) */ /* Pull Enable (pull-down by default) */
#define KINETIS_GPIO_CONFIG_PE_BIT 1 #define KINETIS_GPIO_CONFIG_PE_BIT 1
#define KINETIS_GPIO_CONFIG_PE_MSK (1 << KINETIS_GPIO_CONFIG_PE_BIT) #define KINETIS_GPIO_CONFIG_PE_MSK (1 << KINETIS_GPIO_CONFIG_PE_BIT)
/* Pull Select (0=pull-down, 1=pull-up) */
#define KINETIS_GPIO_CONFIG_PS_BIT 0
#define KINETIS_GPIO_CONFIG_PS_MSK (1 << KINETIS_GPIO_CONFIG_PS_BIT)
/* Drive Strength Enable (high drive strength) */ /* Drive Strength Enable (high drive strength) */
#define KINETIS_GPIO_CONFIG_DSE_MSK (1 << 6) #define KINETIS_GPIO_CONFIG_DSE_MSK (1 << 6)
...@@ -44,6 +47,10 @@ ...@@ -44,6 +47,10 @@
/* Also enable the pull-down register */ /* Also enable the pull-down register */
#define KINETIS_GPIO_CONFIG_PULLDOWN(mux) \ #define KINETIS_GPIO_CONFIG_PULLDOWN(mux) \
(KINETIS_GPIO_CONFIG_MUX(mux) | KINETIS_GPIO_CONFIG_PE_MSK) (KINETIS_GPIO_CONFIG_MUX(mux) | KINETIS_GPIO_CONFIG_PE_MSK)
/* Also enable the pull-up register */
#define KINETIS_GPIO_CONFIG_PULLUP(mux) \
(KINETIS_GPIO_CONFIG_MUX(mux) | \
KINETIS_GPIO_CONFIG_PE_MSK | KINETIS_GPIO_CONFIG_PS_MSK)
/* Also enable high drive strength */ /* Also enable high drive strength */
#define KINETIS_GPIO_CONFIG_DSE(mux) \ #define KINETIS_GPIO_CONFIG_DSE(mux) \
(KINETIS_GPIO_CONFIG_MUX(mux) | KINETIS_GPIO_CONFIG_DSE_MSK) (KINETIS_GPIO_CONFIG_MUX(mux) | KINETIS_GPIO_CONFIG_DSE_MSK)
......
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