Commit f1871ce9 authored by Sergei Miroshnichenko's avatar Sergei Miroshnichenko

RM#1046 stm32: qspi: Add support for QSPI iomux

parent c30a7477
......@@ -348,6 +348,23 @@ static const struct stm32f2_gpio_dsc ltdc_iomux[] = {
};
#endif /* CONFIG_VIDEO_STM32F4_LTDC */
#ifdef CONFIG_STM32_QSPI
# ifdef CONFIG_SYS_STM32F769I_DISCO
static const struct stm32f2_gpio_dsc qspi_af9_iomux[] = {
{STM32F2_GPIO_PORT_C, STM32F2_GPIO_PIN_9}, /* D0 */
{STM32F2_GPIO_PORT_C, STM32F2_GPIO_PIN_10}, /* D1 */
{STM32F2_GPIO_PORT_E, STM32F2_GPIO_PIN_2}, /* D2 */
{STM32F2_GPIO_PORT_D, STM32F2_GPIO_PIN_13}, /* D3 */
{STM32F2_GPIO_PORT_B, STM32F2_GPIO_PIN_2}, /* CLK */
};
static const struct stm32f2_gpio_dsc qspi_af10_iomux[] = {
{STM32F2_GPIO_PORT_B, STM32F2_GPIO_PIN_6}, /* NCS */
};
# else
# error "QSPI is not defined for this platform"
# endif
#endif /* CONFIG_STM32_QSPI */
#ifdef CONFIG_SYS_BOARD_UCL_BSB
/*
* Configure GPIOs
......@@ -421,6 +438,29 @@ static int ltdc_setup_iomux(void)
}
#endif /* CONFIG_VIDEO_STM32F4_LTDC */
static int qspi_setup_iomux(void)
{
int rv = 0;
#ifdef CONFIG_STM32_QSPI
int i;
for (i = 0; i < ARRAY_SIZE(qspi_af9_iomux); i++) {
rv = stm32f2_gpio_config(&qspi_af9_iomux[i],
STM32F2_GPIO_ROLE_QSPI_AF9);
if (rv)
break;
}
for (i = 0; i < ARRAY_SIZE(qspi_af10_iomux); i++) {
rv = stm32f2_gpio_config(&qspi_af10_iomux[i],
STM32F2_GPIO_ROLE_QSPI_AF10);
if (rv)
break;
}
#endif /* CONFIG_STM32_QSPI */
return rv;
}
/*
* Early hardware init.
*/
......@@ -463,6 +503,10 @@ int board_init(void)
return rv;
#endif /* CONFIG_VIDEO_STM32F4_LTDC */
rv = qspi_setup_iomux();
if (rv)
return rv;
Done:
return 0;
}
......
......@@ -106,6 +106,9 @@ DECLARE_GLOBAL_DATA_PTR;
*/
#define STM32F2_GPIO_AF_LTDC 0x0E
#define STM32F2_GPIO_AF_QSPI9 0x09
#define STM32F2_GPIO_AF_QSPI10 0x0A
/*
* GPIO register map
*/
......@@ -141,7 +144,9 @@ static const u32 af_val[STM32F2_GPIO_ROLE_LAST] = {
(u32)-1,
STM32F2_GPIO_AF_LTDC,
STM32F2_GPIO_AF_FSMC,
(u32)-1
(u32)-1,
STM32F2_GPIO_AF_QSPI9, /* STM32F2_GPIO_ROLE_QSPI_AF9 */
STM32F2_GPIO_AF_QSPI10, /* STM32F2_GPIO_ROLE_QSPI_AF10 */
};
/*
......@@ -187,6 +192,8 @@ s32 stm32f2_gpio_config(const struct stm32f2_gpio_dsc *dsc,
case STM32F2_GPIO_ROLE_ETHERNET:
case STM32F2_GPIO_ROLE_MCO:
case STM32F2_GPIO_ROLE_FSMC:
case STM32F2_GPIO_ROLE_QSPI_AF9:
case STM32F2_GPIO_ROLE_QSPI_AF10:
otype = STM32F2_GPIO_OTYPE_PP;
ospeed = STM32F2_GPIO_SPEED_100M;
pupd = STM32F2_GPIO_PUPD_NO;
......
......@@ -77,6 +77,8 @@ enum stm32f2_gpio_role {
STM32F2_GPIO_ROLE_FSMC, /* FSMC static memory controller */
STM32F2_GPIO_ROLE_FMC = STM32F2_GPIO_ROLE_FSMC,
STM32F2_GPIO_ROLE_GPOUT, /* GPOUT */
STM32F2_GPIO_ROLE_QSPI_AF9,
STM32F2_GPIO_ROLE_QSPI_AF10,
STM32F2_GPIO_ROLE_LAST /* for internal usage, must be last */
};
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment