1. 20 Apr, 2012 1 commit
  2. 20 Feb, 2012 1 commit
  3. 30 Jan, 2012 1 commit
    • Alexander Potashev's avatar
      RT75957. twr-k70f120m: configure the DDR controller for synchronous mode · 514d2c27
      Alexander Potashev authored
      There are 3 ports (port 0, port 1, port 2) between the AHB bus and the
      DDR controller. All of these ports are switched to the synchronous mode
      in this patch.
      
      Any of these 3 ports can work in the synchronous mode only when the
      system clock is sourced from PLL1. Since the DDR clock is also sourced
      from the PLL1 and the CPU clock rate is limited to 120 MHz, we have to
      lower the DDR clock to the same 120 MHz.
      
      The source code is configurable so that you can easily switch back to
      the DDR asynchronous mode:
       * Synchronous mode configuration (see include/configs/twr-k70f120m.h):
          * KINETIS_PLL1_VDIV = 24 (we have to limit DDR clock to 120 MHz)
          * KINETIS_MCGOUT_PLL1 is set (system clock is sourced from PLL1)
          * CONFIG_KINETIS_DDR_SYNC is set
       * Asynchronous mode configuration (see include/configs/twr-k70f120m.h):
          * KINETIS_PLL1_VDIV = 30 (we want the maximum DDR clock: 150 MHz)
          * KINETIS_MCGOUT_PLL1 is not set (system clock is sourced from PLL0)
          * CONFIG_KINETIS_DDR_SYNC is not set
      
      The DDR synchronous mode improves performance: 37.27 BogoMIPS in
      synchronous mode (DDR @ 120 MHz) against 11.03 BogoMIPS in asynchronous
      mode (DDR @ 150 MHz) in Linux.
      514d2c27
  4. 25 Jan, 2012 1 commit
    • Alexander Potashev's avatar
      RT75957. twr-k70f120m: NAND Flash support; environment in flash · 7de399c1
      Alexander Potashev authored
      This patch consists of the following:
      1. NAND Flash Controller (NFC) pin configuration.
      2. NFC clock configuration (enable the clock, initialize the clock rate.)
      3. Changes to the `fsl_nfc` NFC driver:
           * Code cleanup (there were compilation warnings, e.g. unused data
               and functions.)
           * `#include <asm/immap.h>` should not be used on ARM.
           * Disable the GPIO configuration code on ARM.
           * Use `__raw_writel/__raw_readl` instead of `out_be32/in_be32`.
               The registers of the NAND Flash Controller always use the
               same endianness as the MCU core.
           * Make the code in fsl_nfc_get_id() and fsl_nfc_get_status()
               endianness-independent (they were accessing the data from
               32-bit register as an array of u8, this approach is
               endianness-dependent.)
      4. NAND support in the U-Boot configuration file.
      5. Support for environment in the NAND flash in the U-Boot configuration
           file.
      6. Increase the size of the `RAM` memory region to fit the statically
      allocated data for the NAND driver and the U-Boot framework for NAND.
      7de399c1
  5. 17 Jan, 2012 2 commits
    • Alexander Potashev's avatar
      RT75957. twr-k70f120m: configure DDR memory controller · f9fec77e
      Alexander Potashev authored
      Take the DDR controller configuration (including memory timings) from
      the Freescale's sample code package (KINETIS_120MHZ_SC.zip).
      
      Move `struct kinetis_sim_regs` to
      `include/asm-arm/arch-kinetis/kinetis.h`, because the SIM registers
      have to be updated in order to properly configure the DDR controller for
      the given external memory chip.
      
      DDR works in the asynchronous mode.
      
      Set the DDR clock to 150 MHz (using the PLL1).
      
      For the board with external DDR memory, the DDR configuration code
      should be enabled using the CONFIG_KINETIS_DDR configuration option in
      the U-Boot configuration file.
      f9fec77e
    • Alexander Potashev's avatar
      RT75957. twr-k70f120m: customize the Kinetis port for TWR-K70F120M · 34d45f55
      Alexander Potashev authored
      The `board/freescale/twr-k70f120m/board.c` file was copied from
      `board/freescale/twr-k60n512/board.c` without code changes, because the
      Ethernet pin configuration is compatible on these two boards.
      
      `cpu/arm_cortexm3/kinetis/clock.c` was updated to support the MCG
      (Multipurpose Clock Generator) internal structure on K70 @ 120 MHz
      which is different from the MCG on K60 @ 100 MHz.
      
      The U-Boot configuration file (include/configs/twr-k70f120m.h) was
      copied from the corresponding file for the TWR-K60N512 board and
      customized for the TWR-K70F120M board:
          1. UART pins are different
          2. There is external RAM on the TWR-K70F120M board
          3. The in-MCU flash is 1 MB in size
          4. The clock configuration was updated (120 MHz core clock)
          5. The K70 MCU has 6 GPIO ports (instead of 5 ports on K60)
      34d45f55
  6. 04 Jan, 2012 2 commits
    • Alexander Potashev's avatar
      RT74765. twr-k60n512: reuse the `mcffec` Ethernet driver for TWR-K60N512 · aa4e8b78
      Alexander Potashev authored
      Also add the code for:
      1. Enabling the clock gate for the Ethernet module of the MCU,
      2. Pin configuration for RMII.
      3. Disabling the MPU (the Ethernet module will be unable to work with
           the SRAM otherwise.)
      
      The pull-down resistor for the RXER pin is enabled, because this input
      pin is not connected to the PHY on the TWR-K60N512 board by default.
      aa4e8b78
    • Alexander Potashev's avatar
      RT74765. twr-k60n512: the very basic port · b1277b2a
      Alexander Potashev authored
      Stubs for twr-k60n512 port.
      
      The `.kinetis_flash_conf` section is necessary to keep the MCU flash
      unprotected and allow future flash programming.
      
      This port does not work, because the Watchdog Timer is not unlocked and
      the MCU is reset by WDT shortly after start-up.
      b1277b2a
  7. 31 Aug, 2010 1 commit