1. 16 Nov, 2018 1 commit
  2. 28 Sep, 2017 2 commits
  3. 03 Mar, 2017 2 commits
  4. 10 Jan, 2017 1 commit
  5. 29 Dec, 2016 2 commits
  6. 18 Aug, 2015 1 commit
  7. 27 Feb, 2015 3 commits
  8. 26 Feb, 2015 2 commits
  9. 24 Feb, 2015 1 commit
  10. 18 Feb, 2015 2 commits
  11. 27 Jan, 2015 1 commit
  12. 11 Nov, 2013 1 commit
    • Pavel Boldin's avatar
      RT #90499: STM32F4X9-SOM NOR/SDRAM errata 2.8.7 fix · 427d84f4
      Pavel Boldin authored
      Copy image from NOR to SDRAM through On-Chip RAM buffer
      setting SDRAM to Self-Refresh on each copy.
      
      Implement flash_read16, flash_write16 and flash_write_buffer
      to disable/enable SDRAM on flash access.
      
      Start and immediately put SDRAM in self-refresh on start-up for flash
      to work correctly.
      427d84f4
  13. 31 Oct, 2013 1 commit
  14. 24 Oct, 2013 1 commit
  15. 21 Oct, 2013 1 commit
  16. 10 Oct, 2013 1 commit
  17. 06 Jun, 2013 1 commit
  18. 01 Apr, 2013 1 commit
  19. 16 Jan, 2013 1 commit
  20. 23 Nov, 2012 2 commits
  21. 20 Nov, 2012 1 commit
  22. 25 Jun, 2012 1 commit
    • Alexander Potashev's avatar
      RT79078. k70-som: Enable and use the RTC clock for FLL when switching to FBE mode · 0c572f22
      Alexander Potashev authored
       * In order to switch the MCG to the PLL Engaged External mode (PEE
      mode), it must pass the FLL Bypassed External mode (FBE mode) as an
      intermediate step. See section `25.4.1 MCG Mode State Diagram` on page
      656 of the K70 Reference Manual.
       * Enable and use the RTC clock for FLL when switching to the
      FLL Bypassed External mode (FBE mode). We do this in `clock_fei_to_fbe()`
      in `u-boot/cpu/arm_cortexm3/kinetis/clock.c` before switching to
      the FBE mode. This is required, because:
         * In order to switch to the PLL Engaged External mode (PEE mode), we
      must pass the FLL Bypassed External mode (FBE mode).
         * This FBE mode requires that there is a working FLL reference clock.
         * Only OSC0 clock (clock or oscillator at EXTAL0/XTAL0) or RTC clock
      (oscillator at EXTAL32/XTAL32) can be used as reference clock for FLL.
         * In the K**-SOM/DNI-ETH configuration, nothing is connected to
      EXTAL0, therefore we have to use the RTC clock as reference clock
      for FLL in the FBE mode.
       * Use RTC for FLL reference clock only on K**-SOMs, but not for
      TWR-K70F120M. To do that, we add a new U-Boot configuration option
      `KINETIS_FLLREF_RTC` that will control usage of RTC for FLL reference
      clock and define this configuration option only in
      `u-boot/include/configs/k70-som.h`.
       * Use in-MCU 20pF oscillator load.
      0c572f22
  23. 18 Jun, 2012 1 commit
  24. 13 Jun, 2012 1 commit
  25. 21 May, 2012 1 commit
  26. 11 May, 2012 1 commit
    • Alexander Potashev's avatar
      RT77744. lpc4350: Support booting from 16-bit external NOR flash · 9942ae92
      Alexander Potashev authored
       * The Boot ROM bootloader loads only the first 32KBytes of U-Boot image
      from the external 16-bit NOR flash. We make U-Boot load the remaining
      contents of the image.
       * Put all function and data used for bootstrapping in the beginning
      of the U-Boot image in sections `.lpc18xx_image_top_text` and
      `.lpc18xx_image_top_data`.
       * Configure the boot pins to determine the boot source if the relevant
      fields in the One-Time Programmable memory are not set.
       * Configure the remaining EMC pins before reading the whole U-Boot
      image. The Boot ROM bootloader forgets to configure some EMC pins.
       * Reload the U-Boot image from NOR flash only when boot source is
      `EMC 16-bit`.
      9942ae92
  27. 03 May, 2012 1 commit
  28. 24 Apr, 2012 1 commit
    • Alexander Potashev's avatar
      RT77744. lpc4350-eval: Basic port · 55246688
      Alexander Potashev authored
      Support the following features:
       * Serial console on USART0.
       * Common pin configuration functions (needed for USART0).
       * Clock configuration: The Cortex-M4 core runs at 204 MHz.
       * `cptf` command is technically available, but has no effect since there is no
      internal flash on LPC18x0/LPC43x0 MCUs.
       * The lowest SRAM region (128 KB at 0x10000000) is reserved for the currently
      running U-Boot image.
      55246688
  29. 20 Feb, 2012 1 commit
  30. 25 Jan, 2012 2 commits
    • Alexander Potashev's avatar
      RT75957. twr-k70f120m: NAND Flash support; environment in flash · 7de399c1
      Alexander Potashev authored
      This patch consists of the following:
      1. NAND Flash Controller (NFC) pin configuration.
      2. NFC clock configuration (enable the clock, initialize the clock rate.)
      3. Changes to the `fsl_nfc` NFC driver:
           * Code cleanup (there were compilation warnings, e.g. unused data
               and functions.)
           * `#include <asm/immap.h>` should not be used on ARM.
           * Disable the GPIO configuration code on ARM.
           * Use `__raw_writel/__raw_readl` instead of `out_be32/in_be32`.
               The registers of the NAND Flash Controller always use the
               same endianness as the MCU core.
           * Make the code in fsl_nfc_get_id() and fsl_nfc_get_status()
               endianness-independent (they were accessing the data from
               32-bit register as an array of u8, this approach is
               endianness-dependent.)
      4. NAND support in the U-Boot configuration file.
      5. Support for environment in the NAND flash in the U-Boot configuration
           file.
      6. Increase the size of the `RAM` memory region to fit the statically
      allocated data for the NAND driver and the U-Boot framework for NAND.
      7de399c1
    • Alexander Potashev's avatar
      RT75957. kinetis gpio: two macros for Kinetis had `LPC178X_` in their names · f6577e72
      Alexander Potashev authored
      This is a cosmetic change, no changes in behaviour.
      f6577e72
  31. 17 Jan, 2012 1 commit
    • Alexander Potashev's avatar
      RT75957. twr-k70f120m: configure DDR memory controller · f9fec77e
      Alexander Potashev authored
      Take the DDR controller configuration (including memory timings) from
      the Freescale's sample code package (KINETIS_120MHZ_SC.zip).
      
      Move `struct kinetis_sim_regs` to
      `include/asm-arm/arch-kinetis/kinetis.h`, because the SIM registers
      have to be updated in order to properly configure the DDR controller for
      the given external memory chip.
      
      DDR works in the asynchronous mode.
      
      Set the DDR clock to 150 MHz (using the PLL1).
      
      For the board with external DDR memory, the DDR configuration code
      should be enabled using the CONFIG_KINETIS_DDR configuration option in
      the U-Boot configuration file.
      f9fec77e