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Alexander Potashev authored
* In order to switch the MCG to the PLL Engaged External mode (PEE mode), it must pass the FLL Bypassed External mode (FBE mode) as an intermediate step. See section `25.4.1 MCG Mode State Diagram` on page 656 of the K70 Reference Manual. * Enable and use the RTC clock for FLL when switching to the FLL Bypassed External mode (FBE mode). We do this in `clock_fei_to_fbe()` in `u-boot/cpu/arm_cortexm3/kinetis/clock.c` before switching to the FBE mode. This is required, because: * In order to switch to the PLL Engaged External mode (PEE mode), we must pass the FLL Bypassed External mode (FBE mode). * This FBE mode requires that there is a working FLL reference clock. * Only OSC0 clock (clock or oscillator at EXTAL0/XTAL0) or RTC clock (oscillator at EXTAL32/XTAL32) can be used as reference clock for FLL. * In the K**-SOM/DNI-ETH configuration, nothing is connected to EXTAL0, therefore we have to use the RTC clock as reference clock for FLL in the FBE mode. * Use RTC for FLL reference clock only on K**-SOMs, but not for TWR-K70F120M. To do that, we add a new U-Boot configuration option `KINETIS_FLLREF_RTC` that will control usage of RTC for FLL reference clock and define this configuration option only in `u-boot/include/configs/k70-som.h`. * Use in-MCU 20pF oscillator load.
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