• Alexander Potashev's avatar
    RT75957. twr-k70f120m: configure DDR memory controller · f9fec77e
    Alexander Potashev authored
    Take the DDR controller configuration (including memory timings) from
    the Freescale's sample code package (KINETIS_120MHZ_SC.zip).
    Move `struct kinetis_sim_regs` to
    `include/asm-arm/arch-kinetis/kinetis.h`, because the SIM registers
    have to be updated in order to properly configure the DDR controller for
    the given external memory chip.
    DDR works in the asynchronous mode.
    Set the DDR clock to 150 MHz (using the PLL1).
    For the board with external DDR memory, the DDR configuration code
    should be enabled using the CONFIG_KINETIS_DDR configuration option in
    the U-Boot configuration file.
twr-k60n512.h 8.27 KB